self.sync += self.mscratch.eq(0) # 32'hXXXXXXXX;
class Misa:
-
def __init__(self, comb, sync):
self.comb = comb
self.sync = sync
self.comb += self.misa.eq(Cat(cl))
+class Fetch:
+ def __init__(self, comb, sync):
+ self.comb = comb
+ self.sync = sync
+ self.action = Signal(fetch_action, name="fetch_action")
+ self.target_pc = Signal(32, name="fetch_target_pc")
+ self.output_pc = Signal(32, name="fetch_output_pc")
+ self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
+ self.output_state = Signal(fetch_output_state,name="fetch_output_state")
+
+ def get_fetch_action(self, dc, load_store_misaligned, mi,
+ branch_taken, misaligned_jump_target,
+ csr_op_is_valid):
+ c = {}
+ c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
+ c[FOS.empty] = self.action.eq(FA.default)
+ c[FOS.trap] = self.action.eq(FA.ack_trap)
+
+ # illegal instruction -> error trap
+ i= If((dc.act & DA.trap_illegal_instruction) != 0,
+ self.action.eq(FA.error_trap)
+ )
+
+ # ecall / ebreak -> noerror trap
+ i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
+ self.action.eq(FA.noerror_trap))
+
+ # load/store: check alignment, check wait
+ i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
+ If((load_store_misaligned | ~mi.rw_address_valid),
+ self.action.eq(FA.error_trap) # misaligned or invalid addr
+ ).Elif(mi.rw_wait,
+ self.action.eq(FA.wait) # wait
+ ).Else(
+ self.action.eq(FA.default) # ok
+ )
+ )
+
+ # fence
+ i = i.Elif((dc.act & DA.fence) != 0,
+ self.action.eq(FA.fence))
+
+ # branch -> misaligned=error, otherwise jump
+ i = i.Elif((dc.act & DA.branch) != 0,
+ If(misaligned_jump_target,
+ self.action.eq(FA.error_trap)
+ ).Else(
+ self.action.eq(FA.jump)
+ )
+ )
+
+ # jal/jalr -> misaligned=error, otherwise jump
+ i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+ If(misaligned_jump_target,
+ self.action.eq(FA.error_trap)
+ ).Else(
+ self.action.eq(FA.jump)
+ )
+ )
+
+ # csr -> opvalid=ok, else error trap
+ i = i.Elif((dc.act & DA.csr) != 0,
+ If(csr_op_is_valid,
+ self.action.eq(FA.default)
+ ).Else(
+ self.action.eq(FA.error_trap)
+ )
+ )
+
+ c[FOS.valid] = i
+
+ return Case(self.output_state, c)
+
+
class CPU(Module):
"""
"""
)
self.specials += mii
- fetch_act = Signal(fetch_action)
- fetch_target_pc = Signal(32)
- fetch_output_pc = Signal(32)
- fetch_output_instruction = Signal(32)
- fetch_output_st = Signal(fetch_output_state)
+ ft = Fetch(self.comb, self.sync)
fs = Instance("CPUFetchStage", name="fetch_stage",
i_clk=ClockSignal(),
o_memory_interface_fetch_address = mi.fetch_address,
i_memory_interface_fetch_data = mi.fetch_data,
i_memory_interface_fetch_valid = mi.fetch_valid,
- i_fetch_action = fetch_act,
- i_target_pc = fetch_target_pc,
- o_output_pc = fetch_output_pc,
- o_output_instruction = fetch_output_instruction,
- o_output_state = fetch_output_st,
+ i_fetch_action = ft.action,
+ i_target_pc = ft.target_pc,
+ o_output_pc = ft.output_pc,
+ o_output_instruction = ft.output_instruction,
+ o_output_state = ft.output_state,
i_reset_vector = reset_vector,
i_mtvec = mtvec,
)
dc = Decoder()
cd = Instance("CPUDecoder", name="decoder",
- i_instruction = fetch_output_instruction,
+ i_instruction = ft.output_instruction,
o_funct7 = dc.funct7,
o_funct3 = dc.funct3,
o_rd = dc.rd,
self.comb += loaded_value.eq(Cat(b0, b1, b2))
self.comb += mi.rw_active.eq(~self.reset
- & (fetch_output_st == fetch_output_state_valid)
+ & (ft.output_state == FOS.valid)
& ~load_store_misaligned
& ((dc.act & (DA.load | DA.store)) != 0))
lui_auipc_result = Signal(32)
self.comb += lui_auipc_result.eq(Mux(dc.opcode[5],
dc.immediate,
- dc.immediate + fetch_output_pc))
+ dc.immediate + ft.output_pc))
- self.comb += fetch_target_pc.eq(Cat(0,
+ self.comb += ft.target_pc.eq(Cat(0,
Mux(dc.opcode != OP.jalr,
- fetch_output_pc[1:32],
+ ft.output_pc[1:32],
register_rs1[1:32] + dc.immediate[1:32])))
misaligned_jump_target = Signal()
- self.comb += misaligned_jump_target.eq(fetch_target_pc[1])
+ self.comb += misaligned_jump_target.eq(ft.target_pc[1])
branch_arg_a = Signal(32)
branch_arg_b = Signal(32)
csr_op_is_valid = Signal()
+ self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
+ branch_taken, misaligned_jump_target,
+ csr_op_is_valid)
if __name__ == "__main__":
example = CPU()
print(verilog.convert(example,
projects / rv32.git / blobdiff