complete get_fetch_action, move to class Fetch

[rv32.git] / cpu.py

diff --git a/cpu.py b/cpu.py
index d345a0099f8adec77bb4750a20af3c91e8378d54..f2561f14e7bc8794cdcb09897c39f6d2034668b7 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -177,6 +177,69 @@ class Fetch:
         self.output_instruction = Signal(32, name="fetch_ouutput_instruction")
         self.output_state = Signal(fetch_output_state,name="fetch_output_state")
 
+    def get_fetch_action(self, dc, load_store_misaligned, mi,
+                         branch_taken, misaligned_jump_target,
+                         csr_op_is_valid):
+        c = {}
+        c["default"] = self.action.eq(FA.default) # XXX should be 32'XXXXXXXX?
+        c[FOS.empty] = self.action.eq(FA.default)
+        c[FOS.trap] = self.action.eq(FA.ack_trap)
+
+        # illegal instruction -> error trap
+        i= If((dc.act & DA.trap_illegal_instruction) != 0,
+                 self.action.eq(FA.error_trap)
+              )
+
+        # ecall / ebreak -> noerror trap
+        i = i.Elif((dc.act & DA.trap_ecall_ebreak) != 0,
+                 self.action.eq(FA.noerror_trap))
+
+        # load/store: check alignment, check wait
+        i = i.Elif((dc.act & (DA.load | DA.store)) != 0,
+                If((load_store_misaligned | ~mi.rw_address_valid),
+                    self.action.eq(FA.error_trap) # misaligned or invalid addr
+                ).Elif(mi.rw_wait,
+                    self.action.eq(FA.wait) # wait
+                ).Else(
+                    self.action.eq(FA.default) # ok
+                )
+              )
+
+        # fence
+        i = i.Elif((dc.act & DA.fence) != 0,
+                 self.action.eq(FA.fence))
+
+        # branch -> misaligned=error, otherwise jump
+        i = i.Elif((dc.act & DA.branch) != 0,
+                If(misaligned_jump_target,
+                    self.action.eq(FA.error_trap)
+                ).Else(
+                    self.action.eq(FA.jump)
+                )
+              )
+
+        # jal/jalr -> misaligned=error, otherwise jump
+        i = i.Elif((dc.act & (DA.jal | DA.jalr)) != 0,
+                If(misaligned_jump_target,
+                    self.action.eq(FA.error_trap)
+                ).Else(
+                    self.action.eq(FA.jump)
+                )
+              )
+
+        # csr -> opvalid=ok, else error trap
+        i = i.Elif((dc.act & DA.csr) != 0,
+                If(csr_op_is_valid,
+                    self.action.eq(FA.default)
+                ).Else(
+                    self.action.eq(FA.error_trap)
+                )
+              )
+
+        c[FOS.valid] = i
+
+        return Case(self.output_state, c)
+
 
 class CPU(Module):
     """
@@ -214,76 +277,6 @@ class CPU(Module):
         for f in [F3.csrrc, F3.csrrci]: c[f] = ~written_value & previous_value
         return Case(funct3, c)
 
-    def get_fetch_action(self, ft, dc, load_store_misaligned, mi,
-                         branch_taken, misaligned_jump_target,
-                         csr_op_is_valid):
-        c = {}
-    """
-        case(fetch_output_state)
-        `fetch_output_state_empty:
-            get_fetch_action = `fetch_action_default;
-        `fetch_output_state_trap:
-            get_fetch_action = `fetch_action_ack_trap;
-        `fetch_output_state_valid: begin
-            if((decode_action & `decode_action_trap_illegal_instruction) != 0) begin
-                get_fetch_action = `fetch_action_error_trap;
-            end
-            else if((decode_action & `decode_action_trap_ecall_ebreak) != 0) begin
-                get_fetch_action = `fetch_action_noerror_trap;
-            end
-            else if((decode_action & (`decode_action_load | `decode_action_store)) != 0) begin
-                if(load_store_misaligned | ~memory_interface_rw_address_valid) begin
-                    get_fetch_action = `fetch_action_error_trap;
-                end
-                else if(memory_interface_rw_wait) begin
-                    get_fetch_action = `fetch_action_wait;
-                end
-                else begin
-                    get_fetch_action = `fetch_action_default;
-                end
-            end
-            else if((decode_action & `decode_action_fence_i) != 0) begin
-                get_fetch_action = `fetch_action_fence;
-            end
-            else if((decode_action & `decode_action_branch) != 0) begin
-                if(branch_taken) begin
-                    if(misaligned_jump_target) begin
-                        get_fetch_action = `fetch_action_error_trap;
-                    end
-                    else begin
-                        get_fetch_action = `fetch_action_jump;
-                    end
-                end
-                else
-                begin
-                    get_fetch_action = `fetch_action_default;
-                end
-            end
-            else if((decode_action & (`decode_action_jal | `decode_action_jalr)) != 0) begin
-                if(misaligned_jump_target) begin
-                    get_fetch_action = `fetch_action_error_trap;
-                end
-                else begin
-                    get_fetch_action = `fetch_action_jump;
-                end
-            end
-            else if((decode_action & `decode_action_csr) != 0) begin
-                if(csr_op_is_valid)
-                    get_fetch_action = `fetch_action_default;
-                else
-                    get_fetch_action = `fetch_action_error_trap;
-            end
-            else begin
-                get_fetch_action = `fetch_action_default;
-            end
-        end
-        default:
-            get_fetch_action = 32'hXXXXXXXX;
-        endcase
-    end
-    endfunction
-    """
-
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
@@ -453,7 +446,7 @@ class CPU(Module):
         self.comb += loaded_value.eq(Cat(b0, b1, b2))
 
         self.comb += mi.rw_active.eq(~self.reset
-                        & (ft.output_state == fetch_output_state_valid)
+                        & (ft.output_state == FOS.valid)
                         & ~load_store_misaligned
                         & ((dc.act & (DA.load | DA.store)) != 0))
 
@@ -524,6 +517,9 @@ class CPU(Module):
 
         csr_op_is_valid = Signal()
 
+        self.comb += ft.get_fetch_action(dc, load_store_misaligned, mi,
+                                 branch_taken, misaligned_jump_target,
+                                 csr_op_is_valid)
 if __name__ == "__main__":
     example = CPU()
     print(verilog.convert(example,