add Makefile for verilog compilation

[rv32.git] / cpu_decoder.py

diff --git a/cpu_decoder.py b/cpu_decoder.py
index 3f91824316dfbb6d1f4dae702a14230145418d9b..c92fb8898daea15443b74c506b45efc328ed603e 100644 (file)
--- a/cpu_decoder.py
+++ b/cpu_decoder.py
@@ -154,7 +154,7 @@ class CPUDecoder(Module):
         return self._decode_funct3(DA.jalr, [F3.jalr, ])
 
     def calculate_op_action(self):
-        """ decode op action
+        """ decode op action: the arith ops, and, or, add, xor, sr/sl etc.
         """
         c = {}
         immz = Constant(0, 12)
@@ -178,7 +178,7 @@ class CPUDecoder(Module):
         return Case(self.funct3, c)
 
     def calculate_misc_action(self):
-        """ decode misc mem action
+        """ decode misc mem action: fence and fence_i
         """
         c = {}
         immz = Constant(0, 12)
@@ -186,14 +186,14 @@ class CPUDecoder(Module):
         # fence
         c[F3.fence] = \
             If((self.immediate[8:12] == immz) & (self.rs1 == regz) & \
-                                                   (self.rd == regz),
+                                                (self.rd == regz),
                 self.decode_action.eq(DA.fence)
             ).Else(
                 self.decode_action.eq(DA.trap_illegal_instruction))
         # fence.i
         c[F3.fence_i] = \
             If((self.immediate[0:12] == immz) & (self.rs1 == regz) & \
-                                                    (self.rd == regz),
+                                                (self.rd == regz),
                 self.decode_action.eq(DA.fence_i)
             ).Else(
                 self.decode_action.eq(DA.trap_illegal_instruction))
@@ -203,18 +203,18 @@ class CPUDecoder(Module):
         return Case(self.funct3, c)
 
     def calculate_system_action(self):
-        """ decode system action
+        """ decode opcode system: ebreak and csrs
         """
         c = {}
         b1 = Constant(1, 32)
         regz = Constant(0, 5)
         # ebreak
         c[F3.ecall_ebreak] = \
-            If((self.immediate != ~b1) | (self.rs1 != regz) | \
-                                                   (self.rd != regz),
-                self.decode_action.eq(DA.trap_illegal_instruction)
+            If((self.immediate == ~b1) & (self.rs1 == regz) & \
+                                         (self.rd == regz),
+                self.decode_action.eq(DA.trap_ecall_ebreak)
             ).Else(
-                self.decode_action.eq(DA.trap_ecall_ebreak))
+                self.decode_action.eq(DA.trap_illegal_instruction))
         # csrs
         for op in [ F3.csrrw, F3.csrrs, F3.csrrc,
                     F3.csrrwi, F3.csrrsi, F3.csrrci]: