add cpu decode cases

[rv32.git] / cpu_fetch_stage.py

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 7c699bd13cb9645d61523c7b1bfd346b3dadeca0..820591efa2ab76c723b357712ab51f14aa192c69 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -67,7 +67,6 @@ class CPUFetchStage(Module):
         delayed_instruction_valid = Signal(reset=0)
 
         self.sync += delayed_instruction.eq(self.output_instruction)
-        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
                     self.output_instruction.eq(delayed_instruction)