from migen import *
from migen.fhdl import verilog
-from riscvdefs import *
+#from riscvdefs import *
from cpudefs import *
-reset_vector = 32'hXXXXXXXX;
-mtvec = 32'hXXXXXXXX;
class CPUFetchStage(Module):
def __init__(self):
self.clk = ClockSignal()
self.reset = ResetSignal()
+ self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+ self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
#output [31:2] memory_interface_fetch_address,
- self.memory_interface_fetch_address = Signal(32)[2:]
+ self.memory_interface_fetch_address = Signal(32)
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
self.fetch_action = Signal(fetch_action)
self.target_pc = Signal(32)
- self.output_pc = Signal(32, reset=reset_vector)
+ self.output_pc = Signal(32, reset=self.reset_vector)
self.output_instruction = Signal(32)
self.output_state = Signal(fetch_output_state,
- reset=fetch_output_state_empty)
+ reset=FOS.empty)
- self.comb += [
- self.cd_sys.clk.eq(self.clk),
- self.cd_sys.rst.eq(self.reset)
- ]
+ #self.comb += [
+ # self.cd_sys.clk.eq(self.clk),
+ # self.cd_sys.rst.eq(self.reset)
+ #]
- fetch_pc = Signal(32, reset=reset_vector)
+ fetch_pc = Signal(32, reset=self.reset_vector)
- self.sync += If(fetch_action != fetch_action_wait,
- output_pc.eq(fetch_pc)).
- Else( output_pc.eq(output_pc)) # hmmm...
- #self.sync += output_pc.eq((fetch_action == `fetch_action_wait) ?
- # output_pc : fetch_pc);
+ self.sync += If(self.fetch_action != FA.wait,
+ self.output_pc.eq(fetch_pc))
- memory_interface_fetch_address = fetch_pc[2:]
+ self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
- initial output_pc <= reset_vector;
- initial output_state <= `fetch_output_state_empty;
+ #initial output_pc <= self.reset_vector;
+ #initial output_state <= `FOS.empty;
- delayed_instruction = Signal(32, reset=0);
- delayed_instruction_valid = Signal(reset=0);
+ delayed_instruction = Signal(32, reset=0)
+ delayed_instruction_valid = Signal(reset=0)
- self.sync += delayed_instruction.eq(output_instruction)
- self.sync += output_state.eq(fetch_output_state_empty)
+ self.sync += delayed_instruction.eq(self.output_instruction)
self.comb += If(delayed_instruction_valid,
- output_instruction.eq(delayed_instruction)
+ self.output_instruction.eq(delayed_instruction)
).Else(
- output_instruction.eq(memory_interface_fetch_data)
+ self.output_instruction.eq(self.memory_interface_fetch_data)
)
- self.sync += delayed_instruction_valid.eq(fetch_action ==
- fetch_action_wait)
+ self.sync += delayed_instruction_valid.eq(self.fetch_action ==
+ FA.wait)
fc = {
- fetch_action_ack_trap:
- If(memory_interface_fetch_valid,
+ FA.ack_trap:
+ If(self.memory_interface_fetch_valid,
[fetch_pc.eq(fetch_pc + 4),
- output_state.eq(fetch_output_state_valid)]
+ self.output_state.eq(FOS.valid)]
).Else(
- [fetch_pc.eq(mtvec),
- output_state.eq(fetch_output_state_trap)]
+ [fetch_pc.eq(self.mtvec),
+ self.output_state.eq(FOS.trap)]
),
- fetch_action_fence:
- [ fetch_pc.eq(output_pc + 4),
- output_state.eq(fetch_output_state_empty)
+ FA.fence:
+ [ fetch_pc.eq(self.output_pc + 4),
+ self.output_state.eq(FOS.empty)
],
- fetch_action_jump:
- [ fetch_pc.eq(target_pc),
- output_state.eq(fetch_output_state_empty)
+ FA.jump:
+ [ fetch_pc.eq(self.target_pc),
+ self.output_state.eq(FOS.empty)
],
- fetch_action_error_trap,
- [fetch_pc.eq(mtvec),
- output_state.eq(fetch_output_state_empty)
+ FA.error_trap:
+ [fetch_pc.eq(self.mtvec),
+ self.output_state.eq(FOS.empty)
],
- fetch_action_wait:
+ FA.wait:
[fetch_pc.eq(fetch_pc),
- output_state.eq(fetch_output_state_valid)
+ self.output_state.eq(FOS.valid)
]
}
- fc[fetch_action_default] = fc[fetch_action_ack_trap]
- fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
- self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
+ fc[FA.default] = fc[FA.ack_trap]
+ fc[FA.noerror_trap] = fc[FA.error_trap]
+ self.sync += Case(self.fetch_action,
+ fc).makedefault(FA.default)
+if __name__ == "__main__":
+ example = CPUFetchStage()
+ #memory_interface_fetch_address = Signal(32)
+ print(verilog.convert(example,
+ { #example.clk,
+ #example.reset,
+ example.memory_interface_fetch_address,
+ example.memory_interface_fetch_data,
+ example.memory_interface_fetch_valid,
+ example.fetch_action,
+ example.target_pc,
+ example.output_pc,
+ example.output_instruction,
+ example.output_state,
+ example.reset_vector,
+ example.mtvec
+ }))