+if __name__ == "__main__":
+ example = CPUFetchStage()
+ #memory_interface_fetch_address = Signal(32)
+ print(verilog.convert(example,
+ { #example.clk,
+ #example.reset,
+ example.memory_interface_fetch_address,
+ example.memory_interface_fetch_data,
+ example.memory_interface_fetch_valid,
+ example.fetch_action,
+ example.target_pc,
+ example.output_pc,
+ example.output_instruction,
+ example.output_state,
+ example.reset_vector,
+ example.mtvec
+ }))