add Makefile for verilog compilation

[rv32.git] / cpu_fetch_stage.py

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 3eae2adfa03a1e4589eb6f527d68eb6f4363958e..e3a3467284fffa3882a06ec4c6fb2e4dfb6fad3e 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -46,7 +46,7 @@ class CPUFetchStage(Module):
         self.output_pc = Signal(32, reset=self.reset_vector)
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
-                                   reset=fetch_output_state_empty)
+                                   reset=FOS.empty)
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -61,7 +61,7 @@ class CPUFetchStage(Module):
         self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
         #initial output_pc <= self.reset_vector;
-        #initial output_state <= `fetch_output_state_empty;
+        #initial output_state <= `FOS.empty;
 
         delayed_instruction = Signal(32, reset=0)
         delayed_instruction_valid = Signal(reset=0)
@@ -81,26 +81,26 @@ class CPUFetchStage(Module):
             FA.ack_trap:
                 If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
-                    self.output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(FOS.valid)]
                 ).Else(
                    [fetch_pc.eq(self.mtvec),
-                    self.output_state.eq(fetch_output_state_trap)]
+                    self.output_state.eq(FOS.trap)]
                 ),
             FA.fence:
                 [ fetch_pc.eq(self.output_pc + 4),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
             FA.jump:
                 [ fetch_pc.eq(self.target_pc),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
             FA.error_trap:
                    [fetch_pc.eq(self.mtvec),
-                    self.output_state.eq(fetch_output_state_empty)
+                    self.output_state.eq(FOS.empty)
                 ],
             FA.wait:
                    [fetch_pc.eq(fetch_pc),
-                    self.output_state.eq(fetch_output_state_valid)
+                    self.output_state.eq(FOS.valid)
                 ]
         }
         fc[FA.default] = fc[FA.ack_trap]