add Makefile for verilog compilation

[rv32.git] / cpu_fetch_stage.py

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 469b21e48ed9fdb101b909396f0c8322a1c8d6fa..e3a3467284fffa3882a06ec4c6fb2e4dfb6fad3e 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -29,45 +29,44 @@ from migen.fhdl import verilog
 #from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
         #output [31:2] memory_interface_fetch_address,
-        self.memory_interface_fetch_address = Signal(32)[2:]
+        self.memory_interface_fetch_address = Signal(32)
         #input [31:0] memory_interface_fetch_data,
         self.memory_interface_fetch_data = Signal(32)
         self.memory_interface_fetch_valid = Signal()
         self.fetch_action = Signal(fetch_action)
         self.target_pc = Signal(32)
-        self.output_pc = Signal(32, reset=reset_vector)
+        self.output_pc = Signal(32, reset=self.reset_vector)
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
-                                   reset=fetch_output_state_empty)
+                                   reset=FOS.empty)
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
         #    self.cd_sys.rst.eq(self.reset)
         #]
 
-        fetch_pc = Signal(32, reset=reset_vector)
+        fetch_pc = Signal(32, reset=self.reset_vector)
 
-        self.sync += If(fetch_action != fetch_action_wait,
+        self.sync += If(self.fetch_action != FA.wait,
                         self.output_pc.eq(fetch_pc))
 
-        memory_interface_fetch_address = fetch_pc[2:]
+        self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
-        #initial output_pc <= reset_vector;
-        #initial output_state <= `fetch_output_state_empty;
+        #initial output_pc <= self.reset_vector;
+        #initial output_state <= `FOS.empty;
 
         delayed_instruction = Signal(32, reset=0)
         delayed_instruction_valid = Signal(reset=0)
 
         self.sync += delayed_instruction.eq(self.output_instruction)
-        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
                     self.output_instruction.eq(delayed_instruction)
@@ -75,50 +74,54 @@ class CPUFetchStage(Module):
                     self.output_instruction.eq(self.memory_interface_fetch_data)
                 )
 
-        self.sync += delayed_instruction_valid.eq(fetch_action ==
-                                                  fetch_action_wait)
+        self.sync += delayed_instruction_valid.eq(self.fetch_action ==
+                                                  FA.wait)
 
         fc = {
-            fetch_action_ack_trap:
+            FA.ack_trap:
                 If(self.memory_interface_fetch_valid,
                    [fetch_pc.eq(fetch_pc + 4),
-                    self.output_state.eq(fetch_output_state_valid)]
+                    self.output_state.eq(FOS.valid)]
                 ).Else(
-                   [fetch_pc.eq(mtvec),
-                    self.output_state.eq(fetch_output_state_trap)]
+                   [fetch_pc.eq(self.mtvec),
+                    self.output_state.eq(FOS.trap)]
                 ),
-            fetch_action_fence:
+            FA.fence:
                 [ fetch_pc.eq(self.output_pc + 4),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
-            fetch_action_jump:
+            FA.jump:
                 [ fetch_pc.eq(self.target_pc),
-                  self.output_state.eq(fetch_output_state_empty)
+                  self.output_state.eq(FOS.empty)
                 ],
-            fetch_action_error_trap:
-                   [fetch_pc.eq(mtvec),
-                    self.output_state.eq(fetch_output_state_empty)
+            FA.error_trap:
+                   [fetch_pc.eq(self.mtvec),
+                    self.output_state.eq(FOS.empty)
                 ],
-            fetch_action_wait:
+            FA.wait:
                    [fetch_pc.eq(fetch_pc),
-                    self.output_state.eq(fetch_output_state_valid)
+                    self.output_state.eq(FOS.valid)
                 ]
         }
-        fc[fetch_action_default] = fc[fetch_action_ack_trap]
-        fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
+        fc[FA.default] = fc[FA.ack_trap]
+        fc[FA.noerror_trap] = fc[FA.error_trap]
+        self.sync += Case(self.fetch_action,
+                          fc).makedefault(FA.default)
 
 if __name__ == "__main__":
     example = CPUFetchStage()
-    memory_interface_fetch_address = Signal(32)
+    #memory_interface_fetch_address = Signal(32)
     print(verilog.convert(example,
          { #example.clk,
            #example.reset,
-           memory_interface_fetch_address,
+           example.memory_interface_fetch_address,
            example.memory_interface_fetch_data,
            example.memory_interface_fetch_valid,
            example.fetch_action,
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state }))
+           example.output_state,
+           example.reset_vector,
+           example.mtvec
+            }))