adding call out to cpu_memory_interface verilog module in cpu.py

[rv32.git] / cpu_fetch_stage.py

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 469b21e48ed9fdb101b909396f0c8322a1c8d6fa..f3269fb75a9fe890c5e11c9be55c2f7bdcce3e39 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -29,15 +29,13 @@ from migen.fhdl import verilog
 #from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
         #output [31:2] memory_interface_fetch_address,
-        self.memory_interface_fetch_address = Signal(32)[2:]
+        self.memory_interface_fetch_address = Signal(32)
         #input [31:0] memory_interface_fetch_data,
         self.memory_interface_fetch_data = Signal(32)
         self.memory_interface_fetch_valid = Signal()
@@ -47,6 +45,8 @@ class CPUFetchStage(Module):
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -55,10 +55,10 @@ class CPUFetchStage(Module):
 
         fetch_pc = Signal(32, reset=reset_vector)
 
-        self.sync += If(fetch_action != fetch_action_wait,
+        self.sync += If(self.fetch_action != fetch_action_wait,
                         self.output_pc.eq(fetch_pc))
 
-        memory_interface_fetch_address = fetch_pc[2:]
+        self.comb += self.memory_interface_fetch_address.eq(fetch_pc[2:])
 
         #initial output_pc <= reset_vector;
         #initial output_state <= `fetch_output_state_empty;
@@ -67,7 +67,6 @@ class CPUFetchStage(Module):
         delayed_instruction_valid = Signal(reset=0)
 
         self.sync += delayed_instruction.eq(self.output_instruction)
-        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
                     self.output_instruction.eq(delayed_instruction)
@@ -75,7 +74,7 @@ class CPUFetchStage(Module):
                     self.output_instruction.eq(self.memory_interface_fetch_data)
                 )
 
-        self.sync += delayed_instruction_valid.eq(fetch_action ==
+        self.sync += delayed_instruction_valid.eq(self.fetch_action ==
                                                   fetch_action_wait)
 
         fc = {
@@ -106,19 +105,23 @@ class CPUFetchStage(Module):
         }
         fc[fetch_action_default] = fc[fetch_action_ack_trap]
         fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
-        self.sync += Case(fetch_action, fc).makedefault(fetch_action_default)
+        self.sync += Case(self.fetch_action,
+                          fc).makedefault(fetch_action_default)
 
 if __name__ == "__main__":
     example = CPUFetchStage()
-    memory_interface_fetch_address = Signal(32)
+    #memory_interface_fetch_address = Signal(32)
     print(verilog.convert(example,
          { #example.clk,
            #example.reset,
-           memory_interface_fetch_address,
+           example.memory_interface_fetch_address,
            example.memory_interface_fetch_data,
            example.memory_interface_fetch_valid,
            example.fetch_action,
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state }))
+           example.output_state
+           example.reset_vector,
+           example.mtvec
+            }))