adding call out to cpu_memory_interface verilog module in cpu.py

[rv32.git] / cpu_fetch_stage.py

diff --git a/cpu_fetch_stage.py b/cpu_fetch_stage.py
index 7c699bd13cb9645d61523c7b1bfd346b3dadeca0..f3269fb75a9fe890c5e11c9be55c2f7bdcce3e39 100644 (file)
--- a/cpu_fetch_stage.py
+++ b/cpu_fetch_stage.py
@@ -29,8 +29,6 @@ from migen.fhdl import verilog
 #from riscvdefs import *
 from cpudefs import *
 
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
 
 class CPUFetchStage(Module):
     def __init__(self):
@@ -47,6 +45,8 @@ class CPUFetchStage(Module):
         self.output_instruction = Signal(32)
         self.output_state = Signal(fetch_output_state,
                                    reset=fetch_output_state_empty)
+        self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+        self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
 
         #self.comb += [
         #    self.cd_sys.clk.eq(self.clk),
@@ -67,7 +67,6 @@ class CPUFetchStage(Module):
         delayed_instruction_valid = Signal(reset=0)
 
         self.sync += delayed_instruction.eq(self.output_instruction)
-        self.sync += self.output_state.eq(fetch_output_state_empty)
 
         self.comb += If(delayed_instruction_valid,
                     self.output_instruction.eq(delayed_instruction)
@@ -122,4 +121,7 @@ if __name__ == "__main__":
            example.target_pc,
            example.output_pc,
            example.output_instruction,
-           example.output_state }))
+           example.output_state
+           example.reset_vector,
+           example.mtvec
+            }))