#from riscvdefs import *
from cpudefs import *
-reset_vector = 0x0 #32'hXXXXXXXX;
-mtvec = 0x0 # 32'hXXXXXXXX;
class CPUFetchStage(Module):
def __init__(self):
self.output_instruction = Signal(32)
self.output_state = Signal(fetch_output_state,
reset=fetch_output_state_empty)
+ self.reset_vector = Signal(32) #32'hXXXXXXXX; - parameter
+ self.mtvec = Signal(32) # 32'hXXXXXXXX; - parameter
#self.comb += [
# self.cd_sys.clk.eq(self.clk),
delayed_instruction_valid = Signal(reset=0)
self.sync += delayed_instruction.eq(self.output_instruction)
- self.sync += self.output_state.eq(fetch_output_state_empty)
self.comb += If(delayed_instruction_valid,
self.output_instruction.eq(delayed_instruction)
example.target_pc,
example.output_pc,
example.output_instruction,
- example.output_state }))
+ example.output_state
+ example.reset_vector,
+ example.mtvec
+ }))