add Makefile for verilog compilation

[rv32.git] / cpu_handle_trap.py

diff --git a/cpu_handle_trap.py b/cpu_handle_trap.py
index c77be862b9893f5022ea87c2ddca9456495a9fdf..ad4510c2364be3613eb72c24053cc7ef6a3f6888 100644 (file)
--- a/cpu_handle_trap.py
+++ b/cpu_handle_trap.py
@@ -44,31 +44,31 @@ class CPUHandleTrap(Module):
         self.clk = ClockSignal()
         self.reset = ResetSignal()
 
-        self.handle_trap = Signal()
         self.ft_action = Signal(fetch_action)
         self.dc_action = Signal(decode_action)
         self.dc_immediate = Signal(32)
-        self.mcause = Signal(32)
-        self.mepc = Signal()
-        self.mpie = Signal()
         self.mie = Signal()
+        self.new_mie = Signal()
+        self.new_mepc = Signal()
+        self.new_mpie = Signal()
+        self.new_mcause = Signal(32)
         self.ft_output_pc = Signal(32)
         self.load_store_misaligned = Signal()
 
-        s = [self.mpie.eq(self.mie),
-             self.mie.eq(0),
-             self.mepc.eq(Mux(self.ft_action == FA.noerror_trap,
+        s = [self.new_mpie.eq(self.mie),
+             self.new_mie.eq(0),
+             self.new_mepc.eq(Mux(self.ft_action == FA.noerror_trap,
                            self.ft_output_pc + 4,
                            self.ft_output_pc))]
 
         # fetch action ack trap
         i = If(self.ft_action == FA.ack_trap,
-                self.mcause.eq(cause_instruction_access_fault)
+                self.new_mcause.eq(cause_instruction_access_fault)
               )
 
         # ecall/ebreak
         i = i.Elif((self.dc_action & DA.trap_ecall_ebreak) != 0,
-                self.mcause.eq(Mux(self.dc_immediate[0],
+                self.new_mcause.eq(Mux(self.dc_immediate[0],
                                 cause_machine_environment_call,
                                 cause_breakpoint))
               )
@@ -76,44 +76,45 @@ class CPUHandleTrap(Module):
         # load
         i = i.Elif((self.dc_action & DA.load) != 0,
                 If(self.load_store_misaligned,
-                    self.mcause.eq(cause_load_address_misaligned)
+                    self.new_mcause.eq(cause_load_address_misaligned)
                 ).Else(
-                    self.mcause.eq(cause_load_access_fault)
+                    self.new_mcause.eq(cause_load_access_fault)
                 )
               )
 
         # store
         i = i.Elif((self.dc_action & DA.store) != 0,
                 If(self.load_store_misaligned,
-                    self.mcause.eq(cause_store_amo_address_misaligned)
+                    self.new_mcause.eq(cause_store_amo_address_misaligned)
                 ).Else(
-                    self.mcause.eq(cause_store_amo_access_fault)
+                    self.new_mcause.eq(cause_store_amo_access_fault)
                 )
               )
 
         # jal/jalr -> misaligned=error, otherwise jump
         i = i.Elif((self.dc_action & (DA.jal | DA.jalr | DA.branch)) != 0,
-                self.mcause.eq(cause_instruction_address_misaligned)
+                self.new_mcause.eq(cause_instruction_address_misaligned)
               )
 
         # defaults to illegal instruction
-        i = i.Else(self.mcause.eq(cause_illegal_instruction))
+        i = i.Else(self.new_mcause.eq(cause_illegal_instruction))
 
         s.append(i)
 
-        self.sync += If(self.handle_trap, s)
+        self.sync += s
 
 
 if __name__ == "__main__":
     example = CPUHandleTrap()
     print(verilog.convert(example,
          {
-            example.handle_trap,
             example.ft_action,
             example.dc_immediate,
-            example.mcause,
-            example.mpie,
             example.mie,
+            example.new_mcause,
+            example.new_mepc,
+            example.new_mpie,
+            example.new_mie,
             example.ft_output_pc,
             example.load_store_misaligned,
            }))