add Makefile for verilog compilation

[rv32.git] / cpudefs.py

diff --git a/cpudefs.py b/cpudefs.py
index 4edab9706e8dba5dd2b8b54fac6e41a65ce1c0e2..b5217f94a203cd4024a169e1902d0aa561282635 100644 (file)
--- a/cpudefs.py
+++ b/cpudefs.py
@@ -26,19 +26,25 @@
 from migen import Constant
 fetch_action = 3
 
-fetch_action_default = Constant(0x0, fetch_action)
-fetch_action_fence = Constant(0x1, fetch_action)
-fetch_action_jump = Constant(0x2, fetch_action)
-fetch_action_wait = Constant(0x3, fetch_action)
-fetch_action_error_trap = Constant(0x4, fetch_action)
-fetch_action_noerror_trap = Constant(0x5, fetch_action)
-fetch_action_ack_trap = Constant(0x6, fetch_action)
+class FA:
+    """ Fetch action constants
+    """
+    default = Constant(0x0, fetch_action)
+    fence = Constant(0x1, fetch_action)
+    jump = Constant(0x2, fetch_action)
+    wait = Constant(0x3, fetch_action)
+    error_trap = Constant(0x4, fetch_action)
+    noerror_trap = Constant(0x5, fetch_action)
+    ack_trap = Constant(0x6, fetch_action)
 
 fetch_output_state = 2
 
-fetch_output_state_empty = Constant(0x0, fetch_output_state)
-fetch_output_state_valid = Constant(0x1, fetch_output_state)
-fetch_output_state_trap = Constant(0x2, fetch_output_state)
+class FOS:
+    """ Fetch output state constants
+    """
+    empty = Constant(0x0, fetch_output_state)
+    valid = Constant(0x1, fetch_output_state)
+    trap = Constant(0x2, fetch_output_state)
 
 decode_action = 12