+ #self.clk = ClockSignal()
+ #self.reset = ResetSignal()
+ self.tty_write = Signal()
+ self.tty_write_data = Signal(8)
+ self.tty_write_busy = Signal()
+ self.switch_2 = Signal()
+ self.switch_3 = Signal()
+ self.led_1 = Signal()
+ self.led_3 = Signal()
+
+ ram_size = Constant(0x8000)
+ ram_start = Constant(0x10000, 32)
+ reset_vector = Signal(32)
+ mtvec = Signal(32)
+
+ reset_vector.eq(ram_start)
+ mtvec.eq(ram_start + 0x40)
+
+ l = []
+ for i in range(31):
+ l.append(Signal(32, name="register%d" % i))
+ self.registers = Array(l)
+
+ #self.sync += self.registers[0].eq(0)
+ #self.sync += self.registers[1].eq(0)
+
+ memory_interface_fetch_address = Signal(32)[2:]
+ memory_interface_fetch_data = Signal(32)
+ memory_interface_fetch_valid = Signal()
+ memory_interface_rw_address= Signal(32)[2:]
+ memory_interface_rw_byte_mask = Signal(4)
+ memory_interface_rw_read_not_write = Signal()
+ memory_interface_rw_active = Signal()
+ memory_interface_rw_data_in = Signal(32)
+ memory_interface_rw_data_out = Signal(32)
+ memory_interface_rw_address_valid = Signal()
+ memory_interface_rw_wait = Signal()
+
+ mi = Instance("cpu_memory_interface",
+ p_ram_size = ram_size,
+ p_ram_start = ram_start,
+ i_clk=ClockSignal(),
+ i_rst=ResetSignal(),
+ i_fetch_address = memory_interface_fetch_address,
+ o_fetch_data = memory_interface_fetch_data,
+ o_fetch_valid = memory_interface_fetch_valid,
+ i_rw_address = memory_interface_rw_address,
+ i_rw_byte_mask = memory_interface_rw_byte_mask,
+ i_rw_read_not_write = memory_interface_rw_read_not_write,
+ i_rw_active = memory_interface_rw_active,
+ i_rw_data_in = memory_interface_rw_data_in,
+ o_rw_data_out = memory_interface_rw_data_out,
+ o_rw_address_valid = memory_interface_rw_address_valid,
+ o_rw_wait = memory_interface_rw_wait,
+ o_tty_write = self.tty_write,
+ o_tty_write_data = self.tty_write_data,
+ i_tty_write_busy = self.tty_write_busy,
+ i_switch_2 = self.switch_2,
+ i_switch_3 = self.switch_3,
+ o_led_1 = self.led_1,
+ o_led_3 = self.led_3
+ )
+ self.specials += mi