-
- always @(posedge clk or posedge reset) begin
- if(reset) begin
- output_state <= `fetch_output_state_empty;
- end
- else begin
- case(fetch_action)
- `fetch_action_default,
- `fetch_action_ack_trap: begin
- if(memory_interface_fetch_valid) begin
- fetch_pc <= fetch_pc + 4;
- output_state <= `fetch_output_state_valid;
- end
- else begin
- fetch_pc <= mtvec;
- output_state <= `fetch_output_state_trap;
- end
- end
- `fetch_action_fence: begin
- fetch_pc <= output_pc + 4;
- output_state <= `fetch_output_state_empty;
- end
- `fetch_action_jump: begin
- fetch_pc <= target_pc;
- output_state <= `fetch_output_state_empty;
- end
- `fetch_action_error_trap,
- `fetch_action_noerror_trap: begin
- fetch_pc <= mtvec;
- output_state <= `fetch_output_state_empty;
- end
- `fetch_action_wait: begin
- fetch_pc <= fetch_pc;
- output_state <= `fetch_output_state_valid;
- end
- endcase
- end
- end
- endmodule
+
+ fc = {}
+ self.comb += Case(fetch_action, fc)
+ fc[fetch_action_ack_trap] =
+ If(memory_interface_fetch_valid,
+ [fetch_pc.eq(fetch_pc + 4),
+ output_state.eq(fetch_output_state_valid)]
+ ).Else(
+ [fetch_pc.eq(mtvec),
+ output_state.eq(fetch_output_state_trap)]
+ )
+ fc[fetch_action_default] = fc[fetch_action_ack_trap]
+ fc[fetch_action_fence] =
+ [ fetch_pc.eq(output_pc + 4),
+ output_state.eq(fetch_output_state_empty)]
+ fc[fetch_action_jump] =
+ [ fetch_pc.eq(target_pc),
+ output_state.eq(fetch_output_state_empty)]
+ fc[fetch_action_error_trap] =
+ [fetch_pc.eq(mtvec),
+ output_state.eq(fetch_output_state_empty)]
+ fc[fetch_action_noerror_trap] = fc[fetch_action_error_trap]
+ fc[fetch_action_wait] =
+ [fetch_pc.eq(fetch_pc),
+ output_state.eq(fetch_output_state_valid)]
+