split out MStatus to separate module

diff --git a/cpu.py b/cpu.py
index 01b4e23fa85b84a3a3cfc73d15802ec4f71fddff..4b877f499cc9eea1bbdafc3b1303cccc84f3546d 100644 (file)
--- a/cpu.py
+++ b/cpu.py
@@ -58,46 +58,18 @@ class Decoder:
     opcode = Signal(7, name="decoder_opcode")
     act = Signal(decode_action, name="decoder_action")
 
+
 class MStatus:
     def __init__(self, comb, sync):
         self.comb = comb
         self.sync = sync
         self.mpie = Signal(name="mstatus_mpie")
         self.mie = Signal(name="mstatus_mie")
-        self.mprv = Signal(name="mstatus_mprv")
-        self.tsr = Signal(name="mstatus_tsr")
-        self.tw = Signal(name="mstatus_tw")
-        self.tvm = Signal(name="mstatus_tvm")
-        self.mxr = Signal(name="mstatus_mxr")
-        self._sum = Signal(name="mstatus_sum")
-        self.xs = Signal(name="mstatus_xs")
-        self.fs = Signal(name="mstatus_fs")
-        self.mpp = Signal(2, name="mstatus_mpp")
-        self.spp = Signal(name="mstatus_spp")
-        self.spie = Signal(name="mstatus_spie")
-        self.upie = Signal(name="mstatus_upie")
-        self.sie = Signal(name="mstatus_sie")
-        self.uie = Signal(name="mstatus_uie")
-
-        for n in dir(self):
-            if n in ['make', 'mpp', 'comb', 'sync'] or n.startswith("_"):
-                continue
-            self.comb += getattr(self, n).eq(0x0)
-        self.comb += self.mpp.eq(0b11)
+        self.mstatus = Signal(32, name="mstatus")
 
         self.sync += self.mie.eq(0)
         self.sync += self.mpie.eq(0)
-
-    def make(self):
-        return Cat(
-                self.uie, self.sie, Constant(0), self.mie,
-                self.upie, self.spie, Constant(0), self.mpie,
-                self.spp, Constant(0, 2), self.mpp,
-                self.fs, self.xs, self.mprv, self._sum,
-                self.mxr, self.tvm, self.tw, self.tsr,
-                Constant(0, 8),
-                (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
-                )
+        self.sync += self.mstatus.eq(0)
 
 
 class MIE:
@@ -445,7 +417,7 @@ class CPU(Module):
         c[csr_misa     ] = csr_output_value.eq(misa.misa)
         # mstatus
         c[csr_mstatus  ] = [
-            csr_output_value.eq(mstatus.make()),
+            csr_output_value.eq(mstatus.mstatus),
             csr.evaluate_csr_funct3_op(dc.funct3, csr_output_value,
                                                   csr_written_value),
             mstatus.mpie.eq(csr_written_value[7]),
@@ -694,6 +666,13 @@ class CPU(Module):
         misa = Misa(self.comb, self.sync)
         mip = MIP(self.comb, self.sync)
 
+        ms = Instance("CPUMStatus", name="cpu_mstatus",
+            o_mstatus = mstatus.mstatus,
+            i_mpie = mstatus.mpie,
+            i_mie = mstatus.mie)
+
+        self.specials += ms
+
         # CSR decoding
         csr = CSR(self.comb, self.sync, dc, self.regs.rs1)
 

diff --git a/cpu_mstatus.py b/cpu_mstatus.py
new file mode 100644 (file)
index 0000000..6afecc1
--- /dev/null
+++ b/cpu_mstatus.py
@@ -0,0 +1,96 @@
+"""
+/*
+ * Copyright 2018 Jacob Lifshay
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+`timescale 1ns / 1ps
+`include "riscv.vh"
+`include "cpu.vh"
+"""
+
+import string
+from migen import *
+from migen.fhdl import verilog
+from migen.fhdl.structure import _Operator
+
+from riscvdefs import *
+from cpudefs import *
+
+class MStatus:
+    def __init__(self):
+        self.mpie = Signal(name="mstatus_mpie", reset=0)
+        self.mie = Signal(name="mstatus_mie", reset=0)
+        self.mprv = Signal(name="mstatus_mprv", reset=0)
+        self.tsr = Signal(name="mstatus_tsr", reset=0)
+        self.tw = Signal(name="mstatus_tw", reset=0)
+        self.tvm = Signal(name="mstatus_tvm", reset=0)
+        self.mxr = Signal(name="mstatus_mxr", reset=0)
+        self._sum = Signal(name="mstatus_sum", reset=0)
+        self.xs = Signal(name="mstatus_xs", reset=0)
+        self.fs = Signal(name="mstatus_fs", reset=0)
+        self.mpp = Signal(2, name="mstatus_mpp", reset=0b11)
+        self.spp = Signal(name="mstatus_spp", reset=0)
+        self.spie = Signal(name="mstatus_spie", reset=0)
+        self.upie = Signal(name="mstatus_upie", reset=0)
+        self.sie = Signal(name="mstatus_sie", reset=0)
+        self.uie = Signal(name="mstatus_uie", reset=0)
+
+        io = set()
+        for n in dir(self):
+            if n.startswith("_"):
+                continue
+            n = getattr(self, n)
+            if not isinstance(n, Signal):
+                continue
+            io.add(n)
+        self.io = io
+
+
+class CPUMStatus(Module, MStatus):
+
+    def __init__(self):
+        MStatus.__init__(self)
+        Module.__init__(self)
+
+        self.mstatus = Signal(32)
+
+        for io in self.io:
+            if io.name_override != self.mpp.name_override:
+                self.comb += io.eq(0x0)
+        self.comb += self.mpp.eq(0b11)
+        self.comb += self.mstatus.eq(self.make())
+
+        self.io = set({self.mstatus, self.mpie, self.mie})
+
+    def make(self):
+        return Cat(
+                self.uie, self.sie, Constant(0), self.mie,
+                self.upie, self.spie, Constant(0), self.mpie,
+                self.spp, Constant(0, 2), self.mpp,
+                self.fs, self.xs, self.mprv, self._sum,
+                self.mxr, self.tvm, self.tw, self.tsr,
+                Constant(0, 8),
+                (self.xs == Constant(0b11, 2)) | (self.fs == Constant(0b11, 2))
+                )
+
+if __name__ == "__main__":
+    example = CPUMStatus()
+    print(verilog.convert(example, example.io))