self.clk = ClockSignal()
self.reset = ResetSignal()
#output [31:2] memory_interface_fetch_address,
self.clk = ClockSignal()
self.reset = ResetSignal()
#output [31:2] memory_interface_fetch_address,
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
#input [31:0] memory_interface_fetch_data,
self.memory_interface_fetch_data = Signal(32)
self.memory_interface_fetch_valid = Signal()
self.sync += If(self.fetch_action != fetch_action_wait,
self.output_pc.eq(fetch_pc))
self.sync += If(self.fetch_action != fetch_action_wait,
self.output_pc.eq(fetch_pc))
example.memory_interface_fetch_data,
example.memory_interface_fetch_valid,
example.fetch_action,
example.memory_interface_fetch_data,
example.memory_interface_fetch_valid,
example.fetch_action,