src/core/branchpredictor.bsv

   1 /*
   2 Copyright (c) 2013, IIT Madras
   3 All rights reserved.
   4
   5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
   6
   7 *  Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
   8 *  Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
   9 *  Neither the name of IIT Madras  nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
  10
  11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  12 ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
  13 */
  14 package branchpredictor;
  15         /*===== Pacakge imports ===== */
  16         import BRAMCore::*;
  17         import FIFO::*;
  18         import FIFOF::*;
  19         import SpecialFIFOs::*;
  20         import LFSR::*;
  21         import ConfigReg::*;
  22         import DReg::*;
  23                 import Connectable::*;
  24                 import GetPut::*;
  25         /*===== project imports==== */
  26         import defined_types::*;
  27         `include "core_parameters.bsv"
  28         /*========================= */
  29
  30         interface Ifc_branchpredictor;
  31                 interface Put#(Tuple2#(Bit#(3),Bit#(`VADDR))) send_prediction_request;
  32                 interface Get#(Tuple4#(Bit#(3),Bit#(`VADDR),Bit#(`VADDR),Bit#(2))) prediction_response;
  33                 method Action training (Maybe#(Training_data#(`VADDR)) training_data);
  34         endinterface
  35
  36         (*synthesize*)
  37         module mkbranchpredictor(Ifc_branchpredictor);
  38                 let btb_sizebits=valueOf(TLog#(`BTB_DEPTH));
  39                 let tag_sizebits=(`VADDR-(btb_sizebits+2));
  40                 let max_size=tag_sizebits+3;
  41                 BRAM_DUAL_PORT#(Bit#(TLog#(`BTB_DEPTH)),Bit#(`VADDR)) rg_target_addr <- mkBRAMCore2(valueOf(`BTB_DEPTH),False);
  42                 BRAM_DUAL_PORT#(Bit#(TLog#(`BTB_DEPTH)),Bit#(TAdd#(3,TSub#(TSub#(`VADDR, TLog#(`BTB_DEPTH)),2)))) rg_tag <- mkBRAMCore2(valueOf(`BTB_DEPTH),False);
  43                 Reg#(Bit#(TSub#(TSub#(`VADDR,TLog#(`BTB_DEPTH)),2))) training_tag <-mkReg(0);
  44                 Reg#(Bit#(TLog#(`BTB_DEPTH))) training_index <-mkReg(0);
  45                 Reg#(Bool) rg_initialize <-mkReg(True);
  46                 Reg#(Bit#(TAdd#(1,TLog#(`BTB_DEPTH)))) rg_index<-mkReg(0);
  47                 FIFOF#(Tuple2#(Bit#(3),Bit#(`VADDR))) capture_prediction_request <-mkLFIFOF();
  48                 rule initialize_brams(rg_initialize);
  49                         rg_tag.b.put(True,truncate(rg_index),{3'b001,'d0});
  50                         if(rg_index==(`BTB_DEPTH-1))begin
  51                                 rg_initialize<=False;
  52                                 rg_index<=0;
  53                         end
  54                         else
  55                                 rg_index<=rg_index+1;
  56                 endrule
  57                 interface send_prediction_request = interface Put
  58                         method Action put(Tuple2#(Bit#(3),Bit#(`VADDR)) req)if(!rg_initialize);
  59                                 let {epoch,vaddress} = req;
  60                                 `ifdef verbose $display($time,"\tBPU: Prediction Request for Address: %h",vaddress); `endif
  61                                 rg_target_addr.a.put(False,vaddress[btb_sizebits+1:2],?);
  62                                 rg_tag.a.put(False,vaddress[btb_sizebits+1:2],?);
  63                                 capture_prediction_request.enq(req);
  64                         endmethod
  65                 endinterface;
  66                 interface prediction_response = interface Get
  67                         method ActionValue#(Tuple4#(Bit#(3),Bit#(`VADDR),Bit#(`VADDR),Bit#(2))) get if(!rg_initialize);
  68                                 let {epoch,vaddress} = capture_prediction_request.first;
  69                                 Bit#(`VADDR) target_address=rg_target_addr.a.read;
  70                                 let info=rg_tag.a.read;
  71                                 Bit#(TSub#(TSub#(`VADDR,btb_sizebits),2)) tag=info[tag_sizebits-1:0];
  72                                 Bit#(TSub#(TSub#(`VADDR, TLog#(`BTB_DEPTH)),2)) cpu_tag=vaddress[`VADDR-1:btb_sizebits+2];
  73                                 Bit#(1) valid=info[tag_sizebits+2];
  74                                 Bit#(1) tag_match=pack(tag==cpu_tag)&valid;
  75                                 Bit#(2) state=(tag_match==1)?info[tag_sizebits+1:tag_sizebits]:'b01;
  76                                 let x= tuple4(epoch,vaddress,target_address,state);
  77                                 capture_prediction_request.deq;
  78                                 return x;
  79                         endmethod
  80                 endinterface;
  81                 method Action training (Maybe#(Training_data#(`VADDR)) training_data)if(!rg_initialize); //to train the bpu;
  82                         if(training_data matches tagged Valid .td)begin
  83                                 let addr=td.branch_address;
  84                                 Bit#(TLog#(`BTB_DEPTH)) index=td.pc[btb_sizebits+1:2];
  85                                 Bit#(TSub#(TSub#(`VADDR, TLog#(`BTB_DEPTH)),2)) tag=td.pc[`VADDR-1:btb_sizebits+2];
  86                                 `ifdef verbose $display($time,"\tBPU: training for PC: %h JumpAddr: %h index: %d State:",td.pc,addr,index,fshow(td.state)); `endif
  87                                 rg_target_addr.b.put(True,td.pc[btb_sizebits+1:2],addr);
  88                                 rg_tag.b.put(True,td.pc[btb_sizebits+1:2],{1,td.state,tag});
  89                         end
  90                 endmethod
  91         endmodule
  92 endpackage