adding master and slave interface to rgbtll

diff --git a/src/peripherals/rgbttl/rgbttl_dummy.bsv b/src/peripherals/rgbttl/rgbttl_dummy.bsv
index 80fa8c6fde57b25211737a7ce35c94fa3d86457e..a52d5e7db27f36ee367a652d6a0ea0c6dbe3284f 100644 (file)
--- a/src/peripherals/rgbttl/rgbttl_dummy.bsv
+++ b/src/peripherals/rgbttl/rgbttl_dummy.bsv
@@ -32,14 +32,12 @@ package rgbttl_dummy;
   `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
   import GetPut::*;
   `define RGBTTL_WIDTH 18
   `include "instance_defines.bsv"
   import GetPut::*;

-  import ClockDiv::*;
-  import ConcatReg::*;
-  import Semi_FIFOF::*;

   import BUtils ::*;
   import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;
   import BUtils ::*;
   import AXI4_Types::*;
 
   interface Ifc_rgbttl_dummy;

-         interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Master_IFC#(`ADDR, `DATA, `USERSPACE) master;
+           interface AXI4_Slave_IFC#(`ADDR, `DATA, `USERSPACE) slave;

       interface Get#(Bit#(1)) de;
       interface Get#(Bit#(1)) ck;
       interface Get#(Bit#(1)) vs;
       interface Get#(Bit#(1)) de;
       interface Get#(Bit#(1)) ck;
       interface Get#(Bit#(1)) vs;


@@ -49,8 +47,10 @@ package rgbttl_dummy;
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);
 
   (*synthesize*)
   module mkrgbttl_dummy(Ifc_rgbttl_dummy);

-               AXI4_Lite_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
-                            s_xactor<-mkAXI4_Lite_Slave_Xactor();
+               AXI4_Slave_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            s_xactor<-mkAXI4_Slave_Xactor();
+               AXI4_Master_Xactor_IFC#(`ADDR,`DATA, `USERSPACE)
+                            m_xactor<-mkAXI4_Master_Xactor();

 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);
 
       Reg#(Bit#(1)) rg_de <- mkReg(0);
       Reg#(Bit#(1)) rg_ck <- mkReg(0);


@@ -88,6 +88,7 @@ package rgbttl_dummy;
         endmethod
       endinterface;
 
         endmethod
       endinterface;
 

-      interface master=s_xactor.axi_side;
+      interface slave=s_xactor.axi_side;
+      interface master=m_xactor.axi_side;

   endmodule
 endpackage
   endmodule
 endpackage