signal_bundles: add missing file
[sifive-blocks.git] / src / main / scala / devices / pwm / PWMPins.scala
1 // See LICENSE for license details.
2 package sifive.blocks.devices.pwm
3
4 import Chisel._
5 import freechips.rocketchip.config.Field
6 import freechips.rocketchip.coreplex.{HasPeripheryBus, HasInterruptBus}
7 import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
8 import freechips.rocketchip.util.HeterogeneousBag
9 import sifive.blocks.devices.pinctrl.{Pin}
10
11 class PWMSignals[T <: Data] (pingen: ()=> T, val c: PWMParams) extends Bundle {
12
13 val pwm: Vec[T] = Vec(c.ncmp, pingen())
14
15 override def cloneType: this.type =
16 this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
17 }
18
19 class PWMPins[T <: Pin] (pingen: ()=> T, c: PWMParams) extends PWMSignals[T](pingen, c)
20
21 object PWMPinsFromPort {
22 def apply[T <: Pin] (pins: PWMSignals[T], port: PWMPortIO): Unit = {
23 (pins.pwm zip port.port) foreach {case (pin, port) =>
24 pin.outputPin(port)
25 }
26 }
27 }