1 // See LICENSE for license details.
2 package sifive.blocks.devices.spi
5 import chisel3.experimental.{withClockAndReset}
6 import sifive.blocks.devices.pinctrl.{PinCtrl, Pin}
8 class SPIPins[T <: Pin] (pingen: ()=> T, c: SPIParamsBase) extends SPIBundle(c) {
11 val dq = Vec(4, pingen())
12 val cs = Vec(c.csWidth, pingen())
14 override def cloneType: this.type =
15 this.getClass.getConstructors.head.newInstance(pingen, c).asInstanceOf[this.type]
17 def fromSPIPort(spi: SPIPortIO, clock: Clock, reset: Bool,
18 syncStages: Int = 0, driveStrength: Bool = Bool(false)) {
20 withClockAndReset(clock, reset) {
21 sck.outputPin(spi.sck, ds = driveStrength)
23 (dq zip spi.dq).foreach {case (p, s) =>
24 p.outputPin(s.o, pue = Bool(true), ds = driveStrength)
27 s.i := ShiftRegister(p.i.ival, syncStages)
30 (cs zip spi.cs) foreach { case (c, s) =>
31 c.outputPin(s, ds = driveStrength)