src/main/scala/devices/xilinxvc707mig/XilinxVC707MIG.scala

   1 // See LICENSE for license details.
   2 package sifive.blocks.devices.xilinxvc707mig
   3
   4 import Chisel._
   5 import chisel3.experimental.{Analog,attach}
   6 import freechips.rocketchip.amba.axi4._
   7 import freechips.rocketchip.chip._
   8 import freechips.rocketchip.config.Parameters
   9 import freechips.rocketchip.coreplex.CacheBlockBytes
  10 import freechips.rocketchip.diplomacy._
  11 import freechips.rocketchip.tilelink._
  12 import sifive.blocks.ip.xilinx.vc707mig.{VC707MIGIOClocksReset, VC707MIGIODDR, vc707mig}
  13
  14 trait HasXilinxVC707MIGParameters {
  15 }
  16
  17 class XilinxVC707MIGPads extends Bundle with VC707MIGIODDR
  18
  19 class XilinxVC707MIGIO extends Bundle with VC707MIGIODDR
  20                                       with VC707MIGIOClocksReset
  21
  22 class XilinxVC707MIG(implicit p: Parameters) extends LazyModule with HasXilinxVC707MIGParameters {
  23   val device = new MemoryDevice
  24   val node = TLInputNode()
  25   val axi4 = AXI4InternalOutputNode(Seq(AXI4SlavePortParameters(
  26     slaves = Seq(AXI4SlaveParameters(
  27       address = Seq(AddressSet(p(ExtMem).base, p(ExtMem).size-1)),
  28       resources     = device.reg,
  29       regionType    = RegionType.UNCACHED,
  30       executable    = true,
  31       supportsWrite = TransferSizes(1, 256*8),
  32       supportsRead  = TransferSizes(1, 256*8))),
  33     beatBytes = 8)))
  34
  35   val xing    = LazyModule(new TLAsyncCrossing)
  36   val toaxi4  = LazyModule(new TLToAXI4(beatBytes = 8, adapterName = Some("mem"), stripBits = 1))
  37   val indexer = LazyModule(new AXI4IdIndexer(idBits = 4))
  38   val deint   = LazyModule(new AXI4Deinterleaver(p(CacheBlockBytes)))
  39   val yank    = LazyModule(new AXI4UserYanker)
  40   val buffer  = LazyModule(new AXI4Buffer)
  41
  42   xing.node := node
  43   val monitor = (toaxi4.node := xing.node)
  44   axi4 := buffer.node
  45   buffer.node := yank.node
  46   yank.node := deint.node
  47   deint.node := indexer.node
  48   indexer.node := toaxi4.node
  49
  50   lazy val module = new LazyModuleImp(this) {
  51     val io = new Bundle {
  52       val port = new XilinxVC707MIGIO
  53       val tl = node.bundleIn
  54     }
  55
  56     //MIG black box instantiation
  57     val blackbox = Module(new vc707mig)
  58
  59     //pins to top level
  60
  61     //inouts
  62     attach(io.port.ddr3_dq,blackbox.io.ddr3_dq)
  63     attach(io.port.ddr3_dqs_n,blackbox.io.ddr3_dqs_n)
  64     attach(io.port.ddr3_dqs_p,blackbox.io.ddr3_dqs_p)
  65
  66     //outputs
  67     io.port.ddr3_addr         := blackbox.io.ddr3_addr
  68     io.port.ddr3_ba           := blackbox.io.ddr3_ba
  69     io.port.ddr3_ras_n        := blackbox.io.ddr3_ras_n
  70     io.port.ddr3_cas_n        := blackbox.io.ddr3_cas_n
  71     io.port.ddr3_we_n         := blackbox.io.ddr3_we_n
  72     io.port.ddr3_reset_n      := blackbox.io.ddr3_reset_n
  73     io.port.ddr3_ck_p         := blackbox.io.ddr3_ck_p
  74     io.port.ddr3_ck_n         := blackbox.io.ddr3_ck_n
  75     io.port.ddr3_cke          := blackbox.io.ddr3_cke
  76     io.port.ddr3_cs_n         := blackbox.io.ddr3_cs_n
  77     io.port.ddr3_dm           := blackbox.io.ddr3_dm
  78     io.port.ddr3_odt          := blackbox.io.ddr3_odt
  79
  80     //inputs
  81     //NO_BUFFER clock
  82     blackbox.io.sys_clk_i     := io.port.sys_clk_i
  83
  84     //user interface signals
  85     val axi_async = axi4.bundleIn(0)
  86     xing.module.io.in_clock := clock
  87     xing.module.io.in_reset := reset
  88     xing.module.io.out_clock := blackbox.io.ui_clk
  89     xing.module.io.out_reset := blackbox.io.ui_clk_sync_rst
  90     (Seq(toaxi4, indexer, deint, yank, buffer) ++ monitor) foreach { lm =>
  91       lm.module.clock := blackbox.io.ui_clk
  92       lm.module.reset := blackbox.io.ui_clk_sync_rst
  93     }
  94
  95     io.port.ui_clk            := blackbox.io.ui_clk
  96     io.port.ui_clk_sync_rst   := blackbox.io.ui_clk_sync_rst
  97     io.port.mmcm_locked       := blackbox.io.mmcm_locked
  98     blackbox.io.aresetn       := io.port.aresetn
  99     blackbox.io.app_sr_req    := Bool(false)
 100     blackbox.io.app_ref_req   := Bool(false)
 101     blackbox.io.app_zq_req    := Bool(false)
 102     //app_sr_active           := unconnected
 103     //app_ref_ack             := unconnected
 104     //app_zq_ack              := unconnected
 105
 106     //slave AXI interface write address ports
 107     blackbox.io.s_axi_awid    := axi_async.aw.bits.id
 108     blackbox.io.s_axi_awaddr  := axi_async.aw.bits.addr //truncation ??
 109     blackbox.io.s_axi_awlen   := axi_async.aw.bits.len
 110     blackbox.io.s_axi_awsize  := axi_async.aw.bits.size
 111     blackbox.io.s_axi_awburst := axi_async.aw.bits.burst
 112     blackbox.io.s_axi_awlock  := axi_async.aw.bits.lock
 113     blackbox.io.s_axi_awcache := UInt("b0011")
 114     blackbox.io.s_axi_awprot  := axi_async.aw.bits.prot
 115     blackbox.io.s_axi_awqos   := axi_async.aw.bits.qos
 116     blackbox.io.s_axi_awvalid := axi_async.aw.valid
 117     axi_async.aw.ready        := blackbox.io.s_axi_awready
 118
 119     //slave interface write data ports
 120     blackbox.io.s_axi_wdata   := axi_async.w.bits.data
 121     blackbox.io.s_axi_wstrb   := axi_async.w.bits.strb
 122     blackbox.io.s_axi_wlast   := axi_async.w.bits.last
 123     blackbox.io.s_axi_wvalid  := axi_async.w.valid
 124     axi_async.w.ready         := blackbox.io.s_axi_wready
 125
 126     //slave interface write response
 127     blackbox.io.s_axi_bready  := axi_async.b.ready
 128     axi_async.b.bits.id       := blackbox.io.s_axi_bid
 129     axi_async.b.bits.resp     := blackbox.io.s_axi_bresp
 130     axi_async.b.valid         := blackbox.io.s_axi_bvalid
 131
 132     //slave AXI interface read address ports
 133     blackbox.io.s_axi_arid    := axi_async.ar.bits.id
 134     blackbox.io.s_axi_araddr  := axi_async.ar.bits.addr //truncation ??
 135     blackbox.io.s_axi_arlen   := axi_async.ar.bits.len
 136     blackbox.io.s_axi_arsize  := axi_async.ar.bits.size
 137     blackbox.io.s_axi_arburst := axi_async.ar.bits.burst
 138     blackbox.io.s_axi_arlock  := axi_async.ar.bits.lock
 139     blackbox.io.s_axi_arcache := UInt("b0011")
 140     blackbox.io.s_axi_arprot  := axi_async.ar.bits.prot
 141     blackbox.io.s_axi_arqos   := axi_async.ar.bits.qos
 142     blackbox.io.s_axi_arvalid := axi_async.ar.valid
 143     axi_async.ar.ready        := blackbox.io.s_axi_arready
 144
 145     //slace AXI interface read data ports
 146     blackbox.io.s_axi_rready  := axi_async.r.ready
 147     axi_async.r.bits.id       := blackbox.io.s_axi_rid
 148     axi_async.r.bits.data     := blackbox.io.s_axi_rdata
 149     axi_async.r.bits.resp     := blackbox.io.s_axi_rresp
 150     axi_async.r.bits.last     := blackbox.io.s_axi_rlast
 151     axi_async.r.valid         := blackbox.io.s_axi_rvalid
 152
 153     //misc
 154     io.port.init_calib_complete := blackbox.io.init_calib_complete
 155     blackbox.io.sys_rst       :=io.port.sys_rst
 156     //mig.device_temp         :- unconnceted
 157   }
 158 }