1 // See LICENSE for license details.
2 package sifive.blocks.devices.xilinxvc707pciex1
5 import freechips.rocketchip.amba.axi4._
6 import freechips.rocketchip.coreplex.CacheBlockBytes
7 import freechips.rocketchip.config.Parameters
8 import freechips.rocketchip.diplomacy._
9 import freechips.rocketchip.tilelink._
10 import sifive.blocks.ip.xilinx.vc707axi_to_pcie_x1.{VC707AXIToPCIeX1, VC707AXIToPCIeX1IOClocksReset, VC707AXIToPCIeX1IOSerial}
11 import sifive.blocks.ip.xilinx.ibufds_gte2.IBUFDS_GTE2
13 class XilinxVC707PCIeX1Pads extends Bundle with VC707AXIToPCIeX1IOSerial
15 class XilinxVC707PCIeX1IO extends Bundle with VC707AXIToPCIeX1IOSerial
16 with VC707AXIToPCIeX1IOClocksReset {
17 val axi_ctl_aresetn = Bool(INPUT)
18 val REFCLK_rxp = Bool(INPUT)
19 val REFCLK_rxn = Bool(INPUT)
22 class XilinxVC707PCIeX1(implicit p: Parameters) extends LazyModule {
23 val slave = TLAsyncInputNode()
24 val control = TLAsyncInputNode()
25 val master = TLAsyncOutputNode()
26 val intnode = IntOutputNode()
28 val axi_to_pcie_x1 = LazyModule(new VC707AXIToPCIeX1)
30 axi_to_pcie_x1.slave :=
33 AXI4Deinterleaver(p(CacheBlockBytes))(
34 AXI4IdIndexer(idBits=4)(
35 TLToAXI4(beatBytes=8, adapterName = Some("pcie-slave"))(
36 TLAsyncCrossingSink()(
39 axi_to_pcie_x1.control :=
41 AXI4UserYanker(capMaxFlight = Some(2))(
42 TLToAXI4(beatBytes=4)(
43 TLFragmenter(4, p(CacheBlockBytes))(
44 TLAsyncCrossingSink()(
48 TLAsyncCrossingSource()(
51 AXI4UserYanker(capMaxFlight=Some(8))(
53 axi_to_pcie_x1.master)))))
55 intnode := axi_to_pcie_x1.intnode
57 lazy val module = new LazyModuleImp(this) {
59 val port = new XilinxVC707PCIeX1IO
60 val slave_in = slave.bundleIn
61 val control_in = control.bundleIn
62 val master_out = master.bundleOut
63 val interrupt = intnode.bundleOut
66 io.port <> axi_to_pcie_x1.module.io.port
68 //PCIe Reference Clock
69 val ibufds_gte2 = Module(new IBUFDS_GTE2)
70 axi_to_pcie_x1.module.io.REFCLK := ibufds_gte2.io.O
71 ibufds_gte2.io.CEB := UInt(0)
72 ibufds_gte2.io.I := io.port.REFCLK_rxp
73 ibufds_gte2.io.IB := io.port.REFCLK_rxn