projects
/
sifive-blocks.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (from parent 1:
4381e39
)
shiftregs: Use SyncResetSynchronizerShiftReg primitives where appropriate
synchronizers
author
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 17:59:07 +0000
(10:59 -0700)
committer
Megan Wachs
<megan@sifive.com>
Wed, 6 Sep 2017 17:59:07 +0000
(10:59 -0700)
src/main/scala/devices/i2c/I2CPins.scala
patch
|
blob
|
history
src/main/scala/devices/spi/SPIPhysical.scala
patch
|
blob
|
history
src/main/scala/devices/uart/UARTPeriphery.scala
patch
|
blob
|
history
diff --git
a/src/main/scala/devices/i2c/I2CPins.scala
b/src/main/scala/devices/i2c/I2CPins.scala
index 9bbc57605dd2ca6976912328659d99192ba5cf61..6bf40aedd5526975ebfd5fe7ecb186b643927c09 100644
(file)
--- a/
src/main/scala/devices/i2c/I2CPins.scala
+++ b/
src/main/scala/devices/i2c/I2CPins.scala
@@
-3,7
+3,7
@@
package sifive.blocks.devices.i2c
import Chisel._
import chisel3.experimental.{withClockAndReset}
import Chisel._
import chisel3.experimental.{withClockAndReset}
-import freechips.rocketchip.util.Sync
hronizerShiftRegInit
+import freechips.rocketchip.util.Sync
ResetSynchronizerShiftReg
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
import sifive.blocks.devices.pinctrl.{Pin, PinCtrl}
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
@@
-18,12
+18,12
@@
class I2CPins[T <: Pin](pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
withClockAndReset(clock, reset) {
scl.outputPin(i2c.scl.out, pue=true.B, ie = true.B)
scl.o.oe := i2c.scl.oe
- i2c.scl.in := Sync
hronizerShiftRegInit
(scl.i.ival, syncStages, init = Bool(true),
+ i2c.scl.in := Sync
ResetSynchronizerShiftReg
(scl.i.ival, syncStages, init = Bool(true),
name = Some("i2c_scl_sync"))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
name = Some("i2c_scl_sync"))
sda.outputPin(i2c.sda.out, pue=true.B, ie = true.B)
sda.o.oe := i2c.sda.oe
- i2c.sda.in := Sync
hronizerShiftRegInit
(sda.i.ival, syncStages, init = Bool(true),
+ i2c.sda.in := Sync
ResetSynchronizerShiftReg
(sda.i.ival, syncStages, init = Bool(true),
name = Some("i2c_sda_sync"))
}
}
name = Some("i2c_sda_sync"))
}
}
diff --git
a/src/main/scala/devices/spi/SPIPhysical.scala
b/src/main/scala/devices/spi/SPIPhysical.scala
index 25ad882681e73e42b09a10b7f8a117a942dcce35..0336aef8d06b531d055e8e4c9b321f3bc75995d9 100644
(file)
--- a/
src/main/scala/devices/spi/SPIPhysical.scala
+++ b/
src/main/scala/devices/spi/SPIPhysical.scala
@@
-2,7
+2,7
@@
package sifive.blocks.devices.spi
import Chisel._
package sifive.blocks.devices.spi
import Chisel._
-import freechip
chip
s.rocketchip.util.ShiftRegInit
+import freechips.rocketchip.util.ShiftRegInit
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
class SPIMicroOp(c: SPIParamsBase) extends SPIBundle(c) {
val fn = Bits(width = 1)
diff --git
a/src/main/scala/devices/uart/UARTPeriphery.scala
b/src/main/scala/devices/uart/UARTPeriphery.scala
index 01ae55cd9ea18d47401e71ab0c6a94e3b3bd1c48..f29716c8a350f80fe1b23b11b9ef5b76557c46fa 100644
(file)
--- a/
src/main/scala/devices/uart/UARTPeriphery.scala
+++ b/
src/main/scala/devices/uart/UARTPeriphery.scala
@@
-4,7
+4,7
@@
package sifive.blocks.devices.uart
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
import Chisel._
import chisel3.experimental.{withClockAndReset}
import freechips.rocketchip.config.Field
-import freechips.rocketchip.util.Sync
hronizerShiftRegInit
+import freechips.rocketchip.util.Sync
ResetSynchronizerShiftReg
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
import freechips.rocketchip.coreplex.{HasPeripheryBus, PeripheryBusParams, HasInterruptBus}
import freechips.rocketchip.diplomacy.{LazyModule, LazyMultiIOModuleImp}
import sifive.blocks.devices.pinctrl.{Pin}
@@
-51,7
+51,7
@@
class UARTPins[T <: Pin] (pingen: () => T) extends Bundle {
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
withClockAndReset(clock, reset) {
txd.outputPin(uart.txd)
val rxd_t = rxd.inputPin()
- uart.rxd := Sync
hronizerShiftRegInit(rxd_t, n =
syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
+ uart.rxd := Sync
ResetSynchronizerShiftReg(rxd_t,
syncStages, init = Bool(true), name = Some("uart_rxd_sync"))
}
}
}
}
}
}