Makefile

   1 PYTHON3 ?= "python3"
   2
   3 .PHONY: help Makefile gitupdate install run_sim test htmlupload
   4
   5 gitupdate:
   6         git submodule init
   7         git submodule update --init --recursive --remote
   8
   9 mkpinmux:
  10         ./mkpinmux.sh
  11         cp pinmux/ls180/ls180_pins.py src/soc/debug
  12         cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
  13
  14 install: gitupdate develop mkpinmux
  15
  16 # this is now actually part of openpower-isa repository
  17 pywriter:
  18         echo "pywriter is part of openpower-isa, run that instead"
  19
  20 # this is now actually part of openpower-isa repository
  21 svanalysis:
  22         echo "sv_analysis is part of openpower-isa, run that instead"
  23
  24 develop:
  25         python3 setup.py develop # yes, develop, not install
  26
  27 # build and run libresoc litex simulation
  28 run_sim:
  29         python3 src/soc/simple/issuer_verilog.py --disable-svp64 \
  30                         src/soc/litex/florent/libresoc/libresoc.v
  31         python3 src/soc/litex/florent/sim.py --cpu=libresoc
  32
  33 # and with test gpio (useful for XICS IRC testing)
  34 testgpio_run_sim:
  35         python3 src/soc/simple/issuer_verilog.py \
  36                         src/soc/litex/florent/libresoc/libresoc.v \
  37                         --enable-testgpio
  38         python3 src/soc/litex/florent/sim.py --cpu=libresoc \
  39                         --variant=standardjtagtestgpio
  40
  41 ls180_verilog_nopll:
  42         python3 src/soc/simple/issuer_verilog.py \
  43                 --debug=jtag --enable-core --disable-pll \
  44                 --enable-xics --disable-svp64 \
  45                         src/soc/litex/florent/libresoc/libresoc.v
  46
  47 ls180_verilog:
  48         python3 src/soc/simple/issuer_verilog.py \
  49                 --debug=jtag --enable-core --enable-pll \
  50                 --enable-xics --disable-svp64 \
  51                         src/soc/litex/florent/libresoc/libresoc.v
  52
  53 ls180_4k_verilog:
  54         python3 src/soc/simple/issuer_verilog.py \
  55                 --debug=jtag --enable-core --enable-pll \
  56                 --enable-xics --enable-sram4x4kblock --disable-svp64 \
  57                         src/soc/litex/florent/libresoc/libresoc.v
  58
  59 # build microwatt "external core", note that the TLB set size is set to 16
  60 # for I/D-Cache which needs a corresponding alteration of the device-tree
  61 # entries for linux
  62 microwatt_external_core:
  63         python3 src/soc/simple/issuer_verilog.py --microwatt-compat --enable-mmu \
  64             external_core_top.v
  65
  66 microwatt_external_core_spi:
  67         python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
  68             --small-cache \
  69             --enable-mmu \
  70             --pc-reset 0x10000000 \
  71             external_core_top.v
  72
  73 # microwatt-compatible core with smaller cache size (quick. VERSA_ECP5. just)
  74 microwatt_external_core_bram:
  75         python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
  76             --small-cache \
  77             --enable-mmu \
  78             --pc-reset 0xFF000000 \
  79             external_core_top.v
  80
  81 # microwatt-compatible core with larger cache size (experiment on arty)
  82 microwatt_external_core_bram_arty:
  83         python3 src/soc/simple/issuer_verilog.py --microwatt-compat \
  84             --enable-mmu \
  85             --pc-reset 0xFF000000 \
  86             external_core_top.v
  87
  88 # build the litex libresoc SoC without 4k SRAMs
  89 ls180_verilog_build: ls180_verilog
  90         make -C soc/soc/litex/florent ls180
  91
  92 # build the litex libresoc SoC with 4k SRAMs
  93 ls180_4ksram_verilog_build: ls180_4k_verilog
  94         make -C soc/soc/litex/florent ls1804k
  95
  96 # testing (usually done at install time)
  97 test: install
  98         python3 setup.py test # could just run nosetest3...
  99
 100 pypiupload:
 101         $(PYTHON3) setup.py sdist upload
 102
 103 # Minimal makefile for Sphinx documentation
 104 #
 105
 106 # You can set these variables from the command line.
 107 SPHINXOPTS    =
 108 SPHINXBUILD   = sphinx-build
 109 SPHINXPROJ    = Libre-SOC
 110 SOURCEDIR     = .
 111 BUILDDIR      = build
 112
 113 # Put it first so that "make" without argument is like "make help".
 114 help:
 115         @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 116
 117 # copies all documentation to libre-soc (libre-soc admins only)
 118 htmlupload: clean html
 119         rsync -HPavz --delete build/html/* \
 120         libre-soc.org:/var/www/libre-soc.org/docs/soc/
 121
 122 # Catch-all target: route all unknown targets to Sphinx using the new
 123 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
 124 %: Makefile
 125         echo "catch-all falling through to sphinx for document building"
 126         mkdir -p "$(SOURCEDIR)"/src/gen
 127         sphinx-apidoc --ext-autodoc -o "$(SOURCEDIR)"/src/gen ./src/soc
 128         @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
 129