Makefile

   1 PYTHON3 ?= "python3"
   2
   3 .PHONY: help Makefile gitupdate install run_sim test htmlupload
   4
   5 gitupdate:
   6         git submodule init
   7         git submodule update --init --recursive --remote
   8
   9 mkpinmux:
  10         ./mkpinmux.sh
  11         cp pinmux/ls180/ls180_pins.py src/soc/debug
  12         cp pinmux/ls180/ls180_pins.py src/soc/litex/florent/libresoc
  13
  14 install: gitupdate develop mkpinmux svanalysis
  15
  16 pywriter:
  17         python3 src/soc/decoder/pseudo/pywriter.py
  18
  19 svanalysis:
  20         python3 libreriscv/openpower/sv_analysis.py
  21
  22 develop:
  23         python3 setup.py develop # yes, develop, not install
  24
  25 # build and run libresoc litex simulation
  26 run_sim:
  27         python3 src/soc/simple/issuer_verilog.py --disable-svp64 \
  28                         src/soc/litex/florent/libresoc/libresoc.v
  29         python3 src/soc/litex/florent/sim.py --cpu=libresoc
  30
  31 # and with test gpio (useful for XICS IRC testing)
  32 testgpio_run_sim:
  33         python3 src/soc/simple/issuer_verilog.py \
  34                         src/soc/litex/florent/libresoc/libresoc.v \
  35                         --enable-testgpio
  36         python3 src/soc/litex/florent/sim.py --cpu=libresoc \
  37                         --variant=standardjtagtestgpio
  38
  39 ls180_verilog:
  40         python3 src/soc/simple/issuer_verilog.py \
  41                 --debug=jtag --enable-core --enable-pll \
  42                 --enable-xics --disable-svp64 \
  43                         src/soc/litex/florent/libresoc/libresoc.v
  44
  45 ls180_4k_verilog:
  46         python3 src/soc/simple/issuer_verilog.py \
  47                 --debug=jtag --enable-core --enable-pll \
  48                 --enable-xics --enable-sram4x4kblock --disable-svp64 \
  49                         src/soc/litex/florent/libresoc/libresoc.v
  50
  51 # build the litex libresoc SoC without 4k SRAMs
  52 ls180_verilog_build: ls180_verilog
  53         make -C soc/soc/litex/florent ls180
  54
  55 # build the litex libresoc SoC with 4k SRAMs
  56 ls180_4ksram_verilog_build: ls180_4k_verilog
  57         make -C soc/soc/litex/florent ls1804k
  58
  59 # testing (usually done at install time)
  60 test: install
  61         python3 setup.py test # could just run nosetest3...
  62
  63 # Minimal makefile for Sphinx documentation
  64 #
  65
  66 # You can set these variables from the command line.
  67 SPHINXOPTS    =
  68 SPHINXBUILD   = sphinx-build
  69 SPHINXPROJ    = Libre-SOC
  70 SOURCEDIR     = .
  71 BUILDDIR      = build
  72
  73 # Put it first so that "make" without argument is like "make help".
  74 help:
  75         @$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
  76
  77 # copies all documentation to libre-soc (libre-soc admins only)
  78 htmlupload: clean html
  79         rsync -HPavz --delete build/html/* \
  80         libre-soc.org:/var/www/libre-soc.org/docs/soc/
  81
  82 # Catch-all target: route all unknown targets to Sphinx using the new
  83 # "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
  84 %: Makefile
  85         echo "catch-all falling through to sphinx for document building"
  86         mkdir -p "$(SOURCEDIR)"/src/gen
  87         sphinx-apidoc --ext-autodoc -o "$(SOURCEDIR)"/src/gen ./src/soc
  88         @$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
  89