TLB/src/ariane/mmu.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: Florian Zaruba, ETH Zurich
  13 # Date: 19/04/2017
  14 # Description: Memory Management Unit for Ariane, contains TLB and
  15 #              address translation unit. SV39 as defined in RISC-V
  16 #              privilege specification 1.11-WIP
  17
  18 import ariane_pkg::*;
  19 """
  20
  21 from nmigen import Const, Signal, Cat, Module
  22 from ptw import DCacheReqI, DCacheReqO, TLBUpdate, PTE, PTW
  23 from tlb import TLB
  24
  25
  26 PRIV_LVL_M = Const(0b11, 2)
  27 PRIV_LVL_S = Const(0b01, 2)
  28 PRIV_LVL_U = Const(0b00, 2)
  29
  30
  31 class RVException:
  32     def __init__(self):
  33          self.cause = Signal(64) # cause of exception
  34          self.tval = Signal(64) # more info of causing exception
  35                                 # (e.g.: instruction causing it),
  36                                 #        address of LD/ST fault
  37          self.valid = Signal()
  38
  39     def __iter__(self):
  40         yield self.cause
  41         yield self.tval
  42         yield self.valid
  43
  44     def ports(self):
  45         return list(self)
  46
  47
  48 class ICacheReqI:
  49     def __init__(self):
  50         self.fetch_valid = Signal()   # address translation valid
  51         self.fetch_paddr = Signal(64) # physical address in
  52         self.fetch_exception = RVException() // exception occurred during fetch
  53
  54     def __iter__(self):
  55         yield self.fetch_valid
  56         yield self.fetch_paddr
  57         yield from self.fetch_exception
  58
  59     def ports(self):
  60         return list(self)
  61
  62
  63 class ICacheReqO:
  64     def __init__(self):
  65         self.fetch_req = Signal()     # address translation request
  66         self.fetch_vaddr = Signal(64) # virtual address out
  67
  68     def __iter__(self):
  69         yield self.fetch_req
  70         yield self.fetch_vaddr
  71
  72     def ports(self):
  73         return list(self)
  74
  75
  76 class MMU:
  77     def __init__(self, INSTR_TLB_ENTRIES = 4,
  78                        DATA_TLB_ENTRIES  = 4,
  79                        ASID_WIDTH        = 1):
  80         self.flush_i = Signal()
  81         self.enable_translation_i = Signal()
  82         self.en_ld_st_translation_i = Signal() # enable VM translation for LD/ST
  83         # IF interface
  84         self.icache_areq_i = ICacheReqO()
  85         self.icache_areq_o = ICacheReqI()
  86         # LSU interface
  87         # this is a more minimalistic interface because the actual addressing
  88         # logic is handled in the LSU as we distinguish load and stores,
  89         # what we do here is simple address translation
  90         self.misaligned_ex_i = RVException()
  91         self.lsu_req_i = Signal()   # request address translation
  92         self.lsu_vaddr_i = Signal(64) # virtual address in
  93         self.lsu_is_store_i = Signal() # the translation is requested by a store
  94         # if we need to walk the page table we can't grant in the same cycle
  95
  96         # Cycle 0
  97         self.lsu_dtlb_hit_o = Signal() # sent in the same cycle as the request
  98                                        # if translation hits in the DTLB
  99         # Cycle 1
 100         self.lsu_valid_o = Signal()  # translation is valid
 101         self.lsu_paddr_o = Signal(64) # translated address
 102         self.lsu_exception_o = RVException() # addr translate threw exception
 103
 104         # General control signals
 105         self.priv_lvl_i = Signal(2)
 106         self.ld_st_priv_lvl_i = Signal(2)
 107         self.sum_i = Signal()
 108         self.mxr_i = Signal()
 109         # input logic flag_mprv_i,
 110         self.satp_ppn_i = Signal(44)
 111         self.asid_i = Signal(ASID_WIDTH)
 112         self.flush_tlb_i = Signal()
 113         # Performance counters
 114         self.itlb_miss_o = Signal()
 115         self.dtlb_miss_o = Signal()
 116         # PTW memory interface
 117         self.req_port_i = DCacheReqO()
 118         self.req_port_o = DCacheReqI()
 119
 120     def elaborate(self, platform):
 121         iaccess_err = Signal()   # insufficient priv to access instr page
 122         daccess_err = Signal()   # insufficient priv to access data page
 123         ptw_active = Signal()    # PTW is currently walking a page table
 124         walking_instr = Signal() # PTW is walking because of an ITLB miss
 125         ptw_error = Signal()     # PTW threw an exception
 126
 127         update_vaddr = Signal(39)
 128         update_ptw_itlb = TLBUpdate()
 129         update_ptw_dtlb = TLBUpdate()
 130
 131         itlb_lu_access = Signal()
 132         itlb_content = PTE()
 133         itlb_is_2M = Signal()
 134         itlb_is_1G = Signal()
 135         itlb_lu_hit = Signal()
 136
 137         dtlb_lu_access = Signal()
 138         dtlb_content = PTE()
 139         dtlb_is_2M = Signal()
 140         dtlb_is_1G = Signal()
 141         dtlb_lu_hit = Signal()
 142
 143         # Assignments
 144         m.d.comb += [itlb_lu_access.eq(icache_areq_i.fetch_req),
 145                      dtlb_lu_access.eq(lsu_req_i)
 146                     ]
 147
 148
 149         # ITLB
 150         m.submodules.i_tlb = i_tlb = TLB(INSTR_TLB_ENTRIES, ASID_WIDTH)
 151         m.d.comb += [i_tlb.flush_i.eq(flush_tlb_i),
 152                      i_tlb.update_i.eq(update_ptw_itlb),
 153                      i_tlb.lu_access_i.eq(itlb_lu_access),
 154                      i_tlb.lu_asid_i.eq(asid_i),
 155                      i_tlb.lu_vaddr_i.eq(icache_areq_i.fetch_vaddr),
 156                      itlb_content.eq(i_tlb.lu_content_o),
 157                      itlb_is_2M.eq(i_tlb.lu_is_2M_o),
 158                      itlb_is_1G.eq(i_tlb.lu_is_1G_o),
 159                      itlb_lu_hit.eq(i_tlb.lu_hit_o),
 160                     ]
 161
 162         # DTLB
 163         m.submodules.d_tlb = d_tlb = TLB(DATA_TLB_ENTRIES, ASID_WIDTH)
 164         m.d.comb += [d_tlb.flush_i.eq(flush_tlb_i),
 165                      d_tlb.update_i.eq(update_ptw_dtlb),
 166                      d_tlb.lu_access_i.eq(dtlb_lu_access),
 167                      d_tlb.lu_asid_i.eq(asid_i),
 168                      d_tlb.lu_vaddr_i.eq(lsu_vaddr_i),
 169                      dtlb_content.eq(d_tlb.lu_content_o),
 170                      dtlb_is_2M.eq(d_tlb.lu_is_2M_o),
 171                      dtlb_is_1G.eq(d_tlb.lu_is_1G_o),
 172                      dtlb_lu_hit.eq(d_tlb.lu_hit_o),
 173                     ]
 174
 175         # PTW
 176         m.submodules.ptw = ptw = PTW(ASID_WIDTH)
 177         m.d.comb += [ptw_active.eq(ptw.ptw_active_o),
 178                      walking_instr.eq(ptw.walking_instr_o),
 179                      ptw_error.eq(ptw.ptw_error_o),
 180                      ptw.enable_translation_i.eq(enable_translation_i),
 181
 182                      update_vaddr.eq(ptw.update_vaddr_o),
 183                      update_ptw_itlb.eq(ptw.itlb_update_o),
 184                      update_ptw_dtlb.eq(ptw.dtlb_update_o),
 185
 186                      ptw.itlb_access_i.eq(itlb_lu_access),
 187                      ptw.itlb_hit_i.eq(itlb_lu_hit),
 188                      ptw.itlb_vaddr_i.eq(icache_areq_i.fetch_vaddr),
 189
 190                      ptw.dtlb_access_i.eq(dtlb_lu_access),
 191                      ptw.dtlb_hit_i.eq(dtlb_lu_hit),
 192                      ptw.dtlb_vaddr_i.eq(lsu_vaddr_i),
 193
 194                      ptw.req_port_i.eq(req_port_i),
 195                      req_port_o.eq(ptw.req_port_o),
 196                     ]
 197
 198         # ila_1 i_ila_1 (
 199         #     .clk(clk_i), # input wire clk
 200         #     .probe0({req_port_o.address_tag, req_port_o.address_index}),
 201         #     .probe1(req_port_o.data_req), # input wire [63:0]  probe1
 202         #     .probe2(req_port_i.data_gnt), # input wire [0:0]  probe2
 203         #     .probe3(req_port_i.data_rdata), # input wire [0:0]  probe3
 204         #     .probe4(req_port_i.data_rvalid), # input wire [0:0]  probe4
 205         #     .probe5(ptw_error), # input wire [1:0]  probe5
 206         #     .probe6(update_vaddr), # input wire [0:0]  probe6
 207         #     .probe7(update_ptw_itlb.valid), # input wire [0:0]  probe7
 208         #     .probe8(update_ptw_dtlb.valid), # input wire [0:0]  probe8
 209         #     .probe9(dtlb_lu_access), # input wire [0:0]  probe9
 210         #     .probe10(lsu_vaddr_i), # input wire [0:0]  probe10
 211         #     .probe11(dtlb_lu_hit), # input wire [0:0]  probe11
 212         #     .probe12(itlb_lu_access), # input wire [0:0]  probe12
 213         #     .probe13(icache_areq_i.fetch_vaddr), # input wire [0:0]  probe13
 214         #     .probe14(itlb_lu_hit) # input wire [0:0]  probe13
 215         # );
 216
 217         #-----------------------
 218         # Instruction Interface
 219         #-----------------------
 220         # The instruction interface is a simple request response interface
 221         always_comb begin : instr_interface
 222             # MMU disabled: just pass through
 223             icache_areq_o.fetch_valid  = icache_areq_i.fetch_req;
 224             icache_areq_o.fetch_paddr  = icache_areq_i.fetch_vaddr; # play through in case we disabled address translation
 225             # two potential exception sources:
 226             # 1. HPTW threw an exception -> signal with a page fault exception
 227             # 2. We got an access error because of insufficient permissions -> throw an access exception
 228             icache_areq_o.fetch_exception      = '0;
 229             # Check whether we are allowed to access this memory region from a fetch perspective
 230             iaccess_err   = icache_areq_i.fetch_req && (((priv_lvl_i == riscv::PRIV_LVL_U) && ~itlb_content.u)
 231                                                      || ((priv_lvl_i == riscv::PRIV_LVL_S) && itlb_content.u));
 232
 233             # MMU enabled: address from TLB, request delayed until hit. Error when TLB
 234             # hit and no access right or TLB hit and translated address not valid (e.g.
 235             # AXI decode error), or when PTW performs walk due to ITLB miss and raises
 236             # an error.
 237             if (enable_translation_i) begin
 238                 # we work with SV39, so if VM is enabled, check that all bits [63:38] are equal
 239                 if (icache_areq_i.fetch_req && !((&icache_areq_i.fetch_vaddr[63:38]) == 1'b1 || (|icache_areq_i.fetch_vaddr[63:38]) == 1'b0)) begin
 240                     icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, icache_areq_i.fetch_vaddr, 1'b1};
 241                 end
 242
 243                 icache_areq_o.fetch_valid = 1'b0;
 244
 245                 # 4K page
 246                 icache_areq_o.fetch_paddr = {itlb_content.ppn, icache_areq_i.fetch_vaddr[11:0]};
 247                 # Mega page
 248                 if (itlb_is_2M) begin
 249                     icache_areq_o.fetch_paddr[20:12] = icache_areq_i.fetch_vaddr[20:12];
 250                 end
 251                 # Giga page
 252                 if (itlb_is_1G) begin
 253                     icache_areq_o.fetch_paddr[29:12] = icache_areq_i.fetch_vaddr[29:12];
 254                 end
 255
 256                 # ---------
 257                 # ITLB Hit
 258                 # --------
 259                 # if we hit the ITLB output the request signal immediately
 260                 if (itlb_lu_hit) begin
 261                     icache_areq_o.fetch_valid = icache_areq_i.fetch_req;
 262                     # we got an access error
 263                     if (iaccess_err) begin
 264                         # throw a page fault
 265                         icache_areq_o.fetch_exception = {riscv::INSTR_PAGE_FAULT, icache_areq_i.fetch_vaddr, 1'b1};
 266                     end
 267                 end else
 268                 # ---------
 269                 # ITLB Miss
 270                 # ---------
 271                 # watch out for exceptions happening during walking the page table
 272                 if (ptw_active && walking_instr) begin
 273                     icache_areq_o.fetch_valid = ptw_error;
 274                     icache_areq_o.fetch_exception = {riscv::INSTR_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
 275                 end
 276             end
 277         end
 278
 279         #-----------------------
 280         # Data Interface
 281         #-----------------------
 282         logic [63:0] lsu_vaddr_n,     lsu_vaddr_q;
 283         riscv::pte_t dtlb_pte_n,      dtlb_pte_q;
 284         exception_t  misaligned_ex_n, misaligned_ex_q;
 285         logic        lsu_req_n,       lsu_req_q;
 286         logic        lsu_is_store_n,  lsu_is_store_q;
 287         logic        dtlb_hit_n,      dtlb_hit_q;
 288         logic        dtlb_is_2M_n,    dtlb_is_2M_q;
 289         logic        dtlb_is_1G_n,    dtlb_is_1G_q;
 290
 291         # check if we need to do translation or if we are always ready (e.g.: we are not translating anything)
 292         assign lsu_dtlb_hit_o = (en_ld_st_translation_i) ? dtlb_lu_hit :  1'b1;
 293
 294         # The data interface is simpler and only consists of a request/response interface
 295         always_comb begin : data_interface
 296             # save request and DTLB response
 297             lsu_vaddr_n           = lsu_vaddr_i;
 298             lsu_req_n             = lsu_req_i;
 299             misaligned_ex_n       = misaligned_ex_i;
 300             dtlb_pte_n            = dtlb_content;
 301             dtlb_hit_n            = dtlb_lu_hit;
 302             lsu_is_store_n        = lsu_is_store_i;
 303             dtlb_is_2M_n          = dtlb_is_2M;
 304             dtlb_is_1G_n          = dtlb_is_1G;
 305
 306             lsu_paddr_o           = lsu_vaddr_q;
 307             lsu_valid_o           = lsu_req_q;
 308             lsu_exception_o       = misaligned_ex_q;
 309             # mute misaligned exceptions if there is no request otherwise they will throw accidental exceptions
 310             misaligned_ex_n.valid = misaligned_ex_i.valid & lsu_req_i;
 311
 312             # Check if the User flag is set, then we may only access it in supervisor mode
 313             # if SUM is enabled
 314             daccess_err = (ld_st_priv_lvl_i == riscv::PRIV_LVL_S && !sum_i && dtlb_pte_q.u) || # SUM is not set and we are trying to access a user page in supervisor mode
 315                           (ld_st_priv_lvl_i == riscv::PRIV_LVL_U && !dtlb_pte_q.u);            # this is not a user page but we are in user mode and trying to access it
 316             # translation is enabled and no misaligned exception occurred
 317             if (en_ld_st_translation_i && !misaligned_ex_q.valid) begin
 318                 lsu_valid_o = 1'b0;
 319                 # 4K page
 320                 lsu_paddr_o = {dtlb_pte_q.ppn, lsu_vaddr_q[11:0]};
 321                 # Mega page
 322                 if (dtlb_is_2M_q) begin
 323                   lsu_paddr_o[20:12] = lsu_vaddr_q[20:12];
 324                 end
 325                 # Giga page
 326                 if (dtlb_is_1G_q) begin
 327                     lsu_paddr_o[29:12] = lsu_vaddr_q[29:12];
 328                 end
 329                 # ---------
 330                 # DTLB Hit
 331                 # --------
 332                 if (dtlb_hit_q && lsu_req_q) begin
 333                     lsu_valid_o = 1'b1;
 334                     # this is a store
 335                     if (lsu_is_store_q) begin
 336                         # check if the page is write-able and we are not violating privileges
 337                         # also check if the dirty flag is set
 338                         if (!dtlb_pte_q.w || daccess_err || !dtlb_pte_q.d) begin
 339                             lsu_exception_o = {riscv::STORE_PAGE_FAULT, lsu_vaddr_q, 1'b1};
 340                         end
 341
 342                     # this is a load, check for sufficient access privileges - throw a page fault if necessary
 343                     end else if (daccess_err) begin
 344                         lsu_exception_o = {riscv::LOAD_PAGE_FAULT, lsu_vaddr_q, 1'b1};
 345                     end
 346                 end else
 347
 348                 # ---------
 349                 # DTLB Miss
 350                 # ---------
 351                 # watch out for exceptions
 352                 if (ptw_active && !walking_instr) begin
 353                     # page table walker threw an exception
 354                     if (ptw_error) begin
 355                         # an error makes the translation valid
 356                         lsu_valid_o = 1'b1;
 357                         # the page table walker can only throw page faults
 358                         if (lsu_is_store_q) begin
 359                             lsu_exception_o = {riscv::STORE_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
 360                         end else begin
 361                             lsu_exception_o = {riscv::LOAD_PAGE_FAULT, {25'b0, update_vaddr}, 1'b1};
 362                         end
 363                     end
 364                 end
 365             end
 366         end
 367         # ----------
 368         # Registers
 369         # ----------
 370         always_ff @(posedge clk_i or negedge rst_ni) begin
 371             if (~rst_ni) begin
 372                 lsu_vaddr_q      <= '0;
 373                 lsu_req_q        <= '0;
 374                 misaligned_ex_q  <= '0;
 375                 dtlb_pte_q       <= '0;
 376                 dtlb_hit_q       <= '0;
 377                 lsu_is_store_q   <= '0;
 378                 dtlb_is_2M_q     <= '0;
 379                 dtlb_is_1G_q     <= '0;
 380             end else begin
 381                 lsu_vaddr_q      <=  lsu_vaddr_n;
 382                 lsu_req_q        <=  lsu_req_n;
 383                 misaligned_ex_q  <=  misaligned_ex_n;
 384                 dtlb_pte_q       <=  dtlb_pte_n;
 385                 dtlb_hit_q       <=  dtlb_hit_n;
 386                 lsu_is_store_q   <=  lsu_is_store_n;
 387                 dtlb_is_2M_q     <=  dtlb_is_2M_n;
 388                 dtlb_is_1G_q     <=  dtlb_is_1G_n;
 389             end
 390         end
 391     endmodule