TLB/src/ariane/ptw.py

   1 """
   2 # Copyright 2018 ETH Zurich and University of Bologna.
   3 # Copyright and related rights are licensed under the Solderpad Hardware
   4 # License, Version 0.51 (the "License"); you may not use this file except in
   5 # compliance with the License.  You may obtain a copy of the License at
   6 # http:#solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   7 # or agreed to in writing, software, hardware and materials distributed under
   8 # this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   9 # CONDITIONS OF ANY KIND, either express or implied. See the License for the
  10 # specific language governing permissions and limitations under the License.
  11 #
  12 # Author: David Schaffenrath, TU Graz
  13 # Author: Florian Zaruba, ETH Zurich
  14 # Date: 24.4.2017
  15 # Description: Hardware-PTW
  16
  17 /* verilator lint_off WIDTH */
  18 import ariane_pkg::*;
  19
  20 see linux kernel source:
  21
  22 * "arch/riscv/include/asm/page.h"
  23 * "arch/riscv/include/asm/mmu_context.h"
  24 * "arch/riscv/Kconfig" (CONFIG_PAGE_OFFSET)
  25
  26 """
  27
  28 from nmigen import Const, Signal, Cat, Module
  29 from nmigen.hdl.ast import ArrayProxy
  30 from nmigen.cli import verilog, rtlil
  31 from math import log2
  32
  33
  34 DCACHE_SET_ASSOC = 8
  35 CONFIG_L1D_SIZE =  32*1024
  36 DCACHE_INDEX_WIDTH = int(log2(CONFIG_L1D_SIZE / DCACHE_SET_ASSOC))
  37 DCACHE_TAG_WIDTH = 56 - DCACHE_INDEX_WIDTH
  38
  39 ASID_WIDTH = 8
  40
  41
  42 class DCacheReqI:
  43     def __init__(self):
  44         self.address_index = Signal(DCACHE_INDEX_WIDTH)
  45         self.address_tag = Signal(DCACHE_TAG_WIDTH)
  46         self.data_wdata = Signal(64)
  47         self.data_req = Signal()
  48         self.data_we = Signal()
  49         self.data_be = Signal(8)
  50         self.data_size = Signal(2)
  51         self.kill_req = Signal()
  52         self.tag_valid = Signal()
  53
  54     def ports(self):
  55         return [self.address_index, self.address_tag,
  56                 self.data_wdata, self.data_req,
  57                 self.data_we, self.data_be, self.data_size,
  58                 self.kill_req, self.tag_valid,
  59             ]
  60
  61 class DCacheReqO:
  62     def __init__(self):
  63         self.data_gnt = Signal()
  64         self.data_rvalid = Signal()
  65         self.data_rdata = Signal(64) # actually in PTE object format
  66
  67     def ports(self):
  68         return [ self.data_gnt, self.data_rvalid, self.data_rdata]
  69
  70
  71 class PTE: #(RecordObject):
  72     def __init__(self):
  73         self.reserved = Signal(10)
  74         self.ppn = Signal(44)
  75         self.rsw = Signal(2)
  76         self.d = Signal()
  77         self.a = Signal()
  78         self.g = Signal()
  79         self.u = Signal()
  80         self.x = Signal()
  81         self.w = Signal()
  82         self.r = Signal()
  83         self.v = Signal()
  84
  85     def flatten(self):
  86         return Cat(*self.ports())
  87
  88     def eq(self, x):
  89         if isinstance(x, ArrayProxy):
  90             res = []
  91             for o in self.ports():
  92                 i = getattr(x, o.name)
  93                 res.append(i)
  94             x = Cat(*res)
  95         else:
  96             x = x.flatten()
  97         return self.flatten().eq(x)
  98
  99     def ports(self):
 100         return [self.reserved, self.ppn, self.rsw, self.d, self.a, self.g,
 101                 self.u, self.x, self.w, self.r, self.v]
 102
 103
 104 class TLBUpdate:
 105     def __init__(self):
 106         self.valid = Signal()      # valid flag
 107         self.is_2M = Signal()
 108         self.is_1G = Signal()
 109         self.vpn = Signal(27)
 110         self.asid = Signal(ASID_WIDTH)
 111         self.content = PTE()
 112
 113     def flatten(self):
 114         return Cat(*self.ports())
 115
 116     def eq(self, x):
 117         return self.flatten().eq(x.flatten())
 118
 119     def ports(self):
 120         return [self.valid, self.is_2M, self.is_1G, self.vpn, self.asid] + \
 121                 self.content.ports()
 122
 123
 124 # SV39 defines three levels of page tables
 125 LVL1 = Const(0, 2) # defined to 0 so that ptw_lvl default-resets to LVL1
 126 LVL2 = Const(1, 2)
 127 LVL3 = Const(2, 2)
 128
 129
 130 class PTW:
 131     def __init__(self):
 132         self.flush_i = Signal() # flush everything, we need to do this because
 133         # actually everything we do is speculative at this stage
 134         # e.g.: there could be a CSR instruction that changes everything
 135         self.ptw_active_o = Signal(reset=1)    # active if not IDLE
 136         self.walking_instr_o = Signal()        # set when walking for TLB
 137         self.ptw_error_o = Signal()            # set when an error occurred
 138         self.enable_translation_i = Signal()   # CSRs indicate to enable SV39
 139         self.en_ld_st_translation_i = Signal() # enable VM translation for ld/st
 140
 141         self.lsu_is_store_i = Signal()       # translation triggered by store
 142         # PTW memory interface
 143         self.req_port_i = DCacheReqO()
 144         self.req_port_o = DCacheReqI()
 145
 146         # to TLBs, update logic
 147         self.itlb_update_o = TLBUpdate()
 148         self.dtlb_update_o = TLBUpdate()
 149
 150         self.update_vaddr_o = Signal(39)
 151
 152         self.asid_i = Signal(ASID_WIDTH)
 153         # from TLBs
 154         # did we miss?
 155         self.itlb_access_i = Signal()
 156         self.itlb_hit_i = Signal()
 157         self.itlb_vaddr_i = Signal(64)
 158
 159         self.dtlb_access_i = Signal()
 160         self.dtlb_hit_i = Signal()
 161         self.dtlb_vaddr_i = Signal(64)
 162         # from CSR file
 163         self.satp_ppn_i = Signal(44) # ppn from satp
 164         self.mxr_i = Signal()
 165         # Performance counters
 166         self.itlb_miss_o = Signal()
 167         self.dtlb_miss_o = Signal()
 168
 169     def ports(self):
 170         return [self.ptw_active_o, self.walking_instr_o, self.ptw_error_o,
 171                 ]
 172         return [
 173                 self.enable_translation_i, self.en_ld_st_translation_i,
 174                 self.lsu_is_store_i, self.req_port_i, self.req_port_o,
 175                 self.update_vaddr_o,
 176                 self.asid_i,
 177                 self.itlb_access_i, self.itlb_hit_i, self.itlb_vaddr_i,
 178                 self.dtlb_access_i, self.dtlb_hit_i, self.dtlb_vaddr_i,
 179                 self.satp_ppn_i, self.mxr_i,
 180                 self.itlb_miss_o, self.dtlb_miss_o
 181             ] + self.itlb_update_o.ports() + self.dtlb_update_o.ports()
 182
 183     def elaborate(self, platform):
 184         m = Module()
 185
 186         # input registers
 187         data_rvalid = Signal()
 188         data_rdata = Signal(64)
 189
 190         # NOTE: pte decodes the incoming bit-field (data_rdata). data_rdata
 191         # is spec'd in 64-bit binary-format: better to spec as Record?
 192         pte = PTE()
 193         m.d.comb += pte.flatten().eq(data_rdata)
 194
 195         # SV39 defines three levels of page tables
 196         ptw_lvl = Signal(2) # default=0=LVL1 on reset (see above)
 197         ptw_lvl1 = Signal()
 198         ptw_lvl2 = Signal()
 199         ptw_lvl3 = Signal()
 200         m.d.comb += [ptw_lvl1.eq(ptw_lvl == LVL1),
 201                      ptw_lvl2.eq(ptw_lvl == LVL2),
 202                      ptw_lvl3.eq(ptw_lvl == LVL3)]
 203
 204         # is this an instruction page table walk?
 205         is_instr_ptw = Signal()
 206         global_mapping = Signal()
 207         # latched tag signal
 208         tag_valid = Signal()
 209         # register the ASID
 210         tlb_update_asid = Signal(ASID_WIDTH)
 211         # register VPN we need to walk, SV39 defines a 39 bit virtual addr
 212         vaddr = Signal(64)
 213         # 4 byte aligned physical pointer
 214         ptw_pptr = Signal(56)
 215
 216         end = DCACHE_INDEX_WIDTH + DCACHE_TAG_WIDTH
 217         m.d.sync += [
 218             # Assignments
 219             self.update_vaddr_o.eq(vaddr),
 220
 221             self.walking_instr_o.eq(is_instr_ptw),
 222             # directly output the correct physical address
 223             self.req_port_o.address_index.eq(ptw_pptr[0:DCACHE_INDEX_WIDTH]),
 224             self.req_port_o.address_tag.eq(ptw_pptr[DCACHE_INDEX_WIDTH:end]),
 225             # we are never going to kill this request
 226             self.req_port_o.kill_req.eq(0),              # XXX assign comb?
 227             # we are never going to write with the HPTW
 228             self.req_port_o.data_wdata.eq(Const(0, 64)), # XXX assign comb?
 229             # -----------
 230             # TLB Update
 231             # -----------
 232             self.itlb_update_o.vpn.eq(vaddr[12:39]),
 233             self.dtlb_update_o.vpn.eq(vaddr[12:39]),
 234             # update the correct page table level
 235             self.itlb_update_o.is_2M.eq(ptw_lvl2),
 236             self.itlb_update_o.is_1G.eq(ptw_lvl1),
 237             self.dtlb_update_o.is_2M.eq(ptw_lvl2),
 238             self.dtlb_update_o.is_1G.eq(ptw_lvl1),
 239             # output the correct ASID
 240             self.itlb_update_o.asid.eq(tlb_update_asid),
 241             self.dtlb_update_o.asid.eq(tlb_update_asid),
 242             # set the global mapping bit
 243             self.itlb_update_o.content.eq(pte),
 244             self.itlb_update_o.content.g.eq(global_mapping),
 245             self.dtlb_update_o.content.eq(pte),
 246             self.dtlb_update_o.content.g.eq(global_mapping),
 247
 248             self.req_port_o.tag_valid.eq(tag_valid),
 249         ]
 250
 251         #-------------------
 252         # Page table walker
 253         #-------------------
 254         # A virtual address va is translated into a physical address pa as
 255         # follows:
 256         # 1. Let a be sptbr.ppn × PAGESIZE, and let i = LEVELS-1. (For Sv39,
 257         #    PAGESIZE=2^12 and LEVELS=3.)
 258         # 2. Let pte be the value of the PTE at address a+va.vpn[i]×PTESIZE.
 259         #    (For Sv32, PTESIZE=4.)
 260         # 3. If pte.v = 0, or if pte.r = 0 and pte.w = 1, stop and raise an
 261         #    access exception.
 262         # 4. Otherwise, the PTE is valid. If pte.r = 1 or pte.x = 1, go to
 263         #    step 5.  Otherwise, this PTE is a pointer to the next level of
 264         #    the page table.
 265         #    Let i=i-1. If i < 0, stop and raise an access exception.
 266         #    Otherwise, let a = pte.ppn × PAGESIZE and go to step 2.
 267         # 5. A leaf PTE has been found. Determine if the requested memory
 268         #    access is allowed by the pte.r, pte.w, and pte.x bits. If not,
 269         #    stop and raise an access exception. Otherwise, the translation is
 270         #    successful.  Set pte.a to 1, and, if the memory access is a
 271         #    store, set pte.d to 1.
 272         #    The translated physical address is given as follows:
 273         #      - pa.pgoff = va.pgoff.
 274         #      - If i > 0, then this is a superpage translation and
 275         #        pa.ppn[i-1:0] = va.vpn[i-1:0].
 276         #      - pa.ppn[LEVELS-1:i] = pte.ppn[LEVELS-1:i].
 277         # 6. If i > 0 and pa.ppn[i − 1 : 0] != 0, this is a misaligned
 278         #    superpage stop and raise a page-fault exception.
 279
 280         m.d.sync += tag_valid.eq(0)
 281
 282         # default assignments
 283         m.d.comb += [
 284             # PTW memory interface
 285             self.req_port_o.data_req.eq(0),
 286             self.req_port_o.data_be.eq(Const(0xFF, 8)),
 287             self.req_port_o.data_size.eq(Const(0b11, 2)),
 288             self.req_port_o.data_we.eq(0),
 289             self.ptw_error_o.eq(0),
 290             self.itlb_update_o.valid.eq(0),
 291             self.dtlb_update_o.valid.eq(0),
 292
 293             self.itlb_miss_o.eq(0),
 294             self.dtlb_miss_o.eq(0),
 295         ]
 296
 297         # ------------
 298         # State Machine
 299         # ------------
 300
 301         with m.FSM() as fsm:
 302
 303             with m.State("IDLE"):
 304                 self.idle(m, is_instr_ptw, ptw_lvl, global_mapping,
 305                           ptw_pptr, vaddr, tlb_update_asid)
 306
 307             with m.State("WAIT_GRANT"):
 308                 self.grant(m, tag_valid, data_rvalid)
 309
 310             with m.State("PTE_LOOKUP"):
 311                 # we wait for the valid signal
 312                 with m.If(data_rvalid):
 313                     self.lookup(m, pte, ptw_lvl, ptw_lvl1, ptw_lvl2, ptw_lvl3,
 314                                 data_rvalid, global_mapping,
 315                                 is_instr_ptw, ptw_pptr)
 316
 317             # Propagate error to MMU/LSU
 318             with m.State("PROPAGATE_ERROR"):
 319                 m.next = "IDLE"
 320                 m.d.comb += self.ptw_error_o.eq(1)
 321
 322             # wait for the rvalid before going back to IDLE
 323             with m.State("WAIT_RVALID"):
 324                 with m.If(data_rvalid):
 325                     m.next = "IDLE"
 326
 327         m.d.sync += [data_rdata.eq(self.req_port_i.data_rdata),
 328                      data_rvalid.eq(self.req_port_i.data_rvalid)
 329                     ]
 330
 331         return m
 332
 333     def set_grant_state(self, m):
 334         # should we have flushed before we got an rvalid,
 335         # wait for it until going back to IDLE
 336         with m.If(self.flush_i):
 337             with m.If (self.req_port_i.data_gnt):
 338                 m.next = "WAIT_RVALID"
 339             with m.Else():
 340                 m.next = "IDLE"
 341         with m.Else():
 342             m.next = "WAIT_GRANT"
 343
 344     def idle(self, m, is_instr_ptw, ptw_lvl, global_mapping,
 345                           ptw_pptr, vaddr, tlb_update_asid):
 346         # by default we start with the top-most page table
 347         m.d.sync += [is_instr_ptw.eq(0),
 348                      ptw_lvl.eq(LVL1),
 349                      global_mapping.eq(0),
 350                      self.ptw_active_o.eq(0), # deactive (IDLE)
 351                     ]
 352         # work out itlb/dtlb miss
 353         m.d.comb += self.itlb_miss_o.eq(self.enable_translation_i & \
 354                                  self.itlb_access_i & \
 355                                  ~self.itlb_hit_i & \
 356                                  ~self.dtlb_access_i)
 357         m.d.comb += self.dtlb_miss_o.eq(self.en_ld_st_translation_i & \
 358                                         self.dtlb_access_i & \
 359                                         ~self.dtlb_hit_i)
 360         # we got an ITLB miss?
 361         with m.If(self.itlb_miss_o):
 362             pptr = Cat(Const(0, 3), self.itlb_vaddr_i[30:39],
 363                        self.satp_ppn_i)
 364             m.d.sync += [ptw_pptr.eq(pptr),
 365                          is_instr_ptw.eq(1),
 366                          vaddr.eq(self.itlb_vaddr_i),
 367                          tlb_update_asid.eq(self.asid_i),
 368                         ]
 369             self.set_grant_state(m)
 370
 371         # we got a DTLB miss?
 372         with m.Elif(self.dtlb_miss_o):
 373             pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[30:39],
 374                        self.satp_ppn_i)
 375             m.d.sync += [ptw_pptr.eq(pptr),
 376                          vaddr.eq(self.dtlb_vaddr_i),
 377                          tlb_update_asid.eq(self.asid_i),
 378                         ]
 379             self.set_grant_state(m)
 380
 381     def grant(self, m, tag_valid, data_rvalid):
 382         # we've got a data WAIT_GRANT so tell the
 383         # cache that the tag is valid
 384
 385         # send a request out
 386         m.d.comb += self.req_port_o.data_req.eq(1)
 387         # wait for the WAIT_GRANT
 388         with m.If(self.req_port_i.data_gnt):
 389             # send the tag valid signal one cycle later
 390             m.d.sync += tag_valid.eq(1)
 391             # should we have flushed before we got an rvalid,
 392             # wait for it until going back to IDLE
 393             with m.If(self.flush_i):
 394                 with m.If (~data_rvalid):
 395                     m.next = "WAIT_RVALID"
 396                 with m.Else():
 397                     m.next = "IDLE"
 398             with m.Else():
 399                 m.next = "PTE_LOOKUP"
 400
 401     def lookup(self, m, pte, ptw_lvl, ptw_lvl1, ptw_lvl2, ptw_lvl3,
 402                             data_rvalid, global_mapping,
 403                             is_instr_ptw, ptw_pptr):
 404         # temporaries
 405         pte_rx = Signal(reset_less=True)
 406         pte_exe = Signal(reset_less=True)
 407         pte_inv = Signal(reset_less=True)
 408         pte_a = Signal(reset_less=True)
 409         st_wd = Signal(reset_less=True)
 410         m.d.comb += [pte_rx.eq(pte.r | pte.x),
 411                     pte_exe.eq(~pte.x | ~pte.a),
 412                     pte_inv.eq(~pte.v | (~pte.r & pte.w)),
 413                     pte_a.eq(pte.a & (pte.r | (pte.x & self.mxr_i))),
 414                     st_wd.eq(self.lsu_is_store_i & (~pte.w | ~pte.d))]
 415
 416         l1err = Signal(reset_less=True)
 417         l2err = Signal(reset_less=True)
 418         m.d.comb += [l2err.eq((ptw_lvl2) & pte.ppn[0:9] != Const(0, 9)),
 419                      l1err.eq((ptw_lvl1) & pte.ppn[0:18] != Const(0, 18)) ]
 420
 421         # check if the global mapping bit is set
 422         with m.If (pte.g):
 423             m.d.sync += global_mapping.eq(1)
 424
 425         m.next = "IDLE"
 426
 427         # -------------
 428         # Invalid PTE
 429         # -------------
 430         # If pte.v = 0, or if pte.r = 0 and pte.w = 1,
 431         # stop and raise a page-fault exception.
 432         with m.If (pte_inv):
 433             m.next = "PROPAGATE_ERROR"
 434
 435         # -----------
 436         # Valid PTE
 437         # -----------
 438
 439         # it is a valid PTE
 440         # if pte.r = 1 or pte.x = 1 it is a valid PTE
 441         with m.Elif (pte_rx):
 442             # Valid translation found (either 1G, 2M or 4K)
 443             with m.If(is_instr_ptw):
 444                 # ------------
 445                 # Update ITLB
 446                 # ------------
 447                 # If page not executable, we can directly raise error.
 448                 # This doesn't put a useless entry into the TLB.
 449                 # The same idea applies to the access flag since we let
 450                 # the access flag be managed by SW.
 451                 with m.If (pte_exe):
 452                     m.next = "IDLE"
 453                 with m.Else():
 454                     m.d.comb += self.itlb_update_o.valid.eq(1)
 455
 456             with m.Else():
 457                 # ------------
 458                 # Update DTLB
 459                 # ------------
 460                 # Check if the access flag has been set, otherwise
 461                 # throw page-fault and let software handle those bits.
 462                 # If page not readable (there are no write-only pages)
 463                 # directly raise an error. This doesn't put a useless
 464                 # entry into the TLB.
 465                 with m.If(pte_a):
 466                     m.d.comb += self.dtlb_update_o.valid.eq(1)
 467                 with m.Else():
 468                     m.next = "PROPAGATE_ERROR"
 469                 # Request is a store: perform additional checks
 470                 # If the request was a store and the page not
 471                 # write-able, raise an error
 472                 # the same applies if the dirty flag is not set
 473                 with m.If (st_wd):
 474                     m.d.comb += self.dtlb_update_o.valid.eq(0)
 475                     m.next = "PROPAGATE_ERROR"
 476
 477             # check if the ppn is correctly aligned: Case (6)
 478             with m.If(l1err | l2err):
 479                 m.next = "PROPAGATE_ERROR"
 480                 m.d.comb += [self.dtlb_update_o.valid.eq(0),
 481                              self.itlb_update_o.valid.eq(0)]
 482
 483         # this is a pointer to the next TLB level
 484         with m.Else():
 485             # pointer to next level of page table
 486             with m.If (ptw_lvl1):
 487                 # we are in the second level now
 488                 pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[21:30], pte.ppn)
 489                 m.d.sync += [ptw_pptr.eq(pptr),
 490                              ptw_lvl.eq(LVL2)
 491                             ]
 492             with m.If(ptw_lvl2):
 493                 # here we received a pointer to the third level
 494                 pptr = Cat(Const(0, 3), self.dtlb_vaddr_i[12:21], pte.ppn)
 495                 m.d.sync += [ptw_pptr.eq(pptr),
 496                              ptw_lvl.eq(LVL3)
 497                             ]
 498             self.set_grant_state(m)
 499
 500             with m.If (ptw_lvl3):
 501                 # Should already be the last level
 502                 # page table => Error
 503                 m.d.sync += ptw_lvl.eq(LVL3)
 504                 m.next = "PROPAGATE_ERROR"
 505
 506
 507 if __name__ == '__main__':
 508     ptw = PTW()
 509     vl = rtlil.convert(ptw, ports=ptw.ports())
 510     with open("test_ptw.il", "w") as f:
 511         f.write(vl)