TLB/src/ariane/test_ptw.py

   1 from nmigen.compat.sim import run_simulation
   2
   3 from ptw import PTW, PTE
   4
   5
   6 def testbench(dut):
   7
   8     addr = 0x8000000
   9
  10     #pte = PTE()
  11     #yield pte.v.eq(1)
  12     #yield pte.r.eq(1)
  13
  14     yield dut.req_port_i.data_gnt.eq(1)
  15     yield dut.req_port_i.data_rvalid.eq(1)
  16     yield dut.req_port_i.data_rdata.eq(0xc2<<56)#pte.flatten())
  17
  18     # data lookup
  19     yield dut.en_ld_st_translation_i.eq(1)
  20     yield dut.asid_i.eq(1)
  21
  22     yield dut.dtlb_access_i.eq(1)
  23     yield dut.dtlb_hit_i.eq(0)
  24     yield dut.dtlb_vaddr_i.eq(0x400000000)
  25
  26     yield
  27     yield
  28     yield
  29
  30     yield dut.dtlb_access_i.eq(1)
  31     yield dut.dtlb_hit_i.eq(0)
  32     yield dut.dtlb_vaddr_i.eq(0x200000)
  33
  34     yield
  35     yield
  36     yield
  37
  38     yield dut.req_port_i.data_gnt.eq(0)
  39     yield dut.dtlb_access_i.eq(1)
  40     yield dut.dtlb_hit_i.eq(0)
  41     yield dut.dtlb_vaddr_i.eq(0x400000011)
  42
  43     yield
  44     yield dut.req_port_i.data_gnt.eq(1)
  45     yield
  46     yield
  47
  48     # data lookup, PTW levels 1-2-3
  49     addr = 0x4000000
  50     yield dut.dtlb_vaddr_i.eq(addr)
  51     yield dut.mxr_i.eq(0x1)
  52     yield dut.req_port_i.data_gnt.eq(1)
  53     yield dut.req_port_i.data_rvalid.eq(1)
  54     yield dut.req_port_i.data_rdata.eq(0x82<<56 | addr<<2)#pte.flatten())
  55
  56     yield dut.en_ld_st_translation_i.eq(1)
  57     yield dut.asid_i.eq(1)
  58
  59     yield dut.dtlb_access_i.eq(1)
  60     yield dut.dtlb_hit_i.eq(0)
  61     yield dut.dtlb_vaddr_i.eq(addr)
  62
  63     yield
  64     yield
  65     yield
  66     yield
  67     yield
  68     yield
  69     yield
  70     yield
  71
  72     yield dut.req_port_i.data_gnt.eq(0)
  73     yield dut.dtlb_access_i.eq(1)
  74     yield dut.dtlb_hit_i.eq(0)
  75     yield dut.dtlb_vaddr_i.eq(0x400000011)
  76
  77     yield
  78     yield dut.req_port_i.data_gnt.eq(1)
  79     yield
  80     yield
  81     yield
  82     yield
  83
  84
  85     # instruction lookup
  86     yield dut.en_ld_st_translation_i.eq(0)
  87     yield dut.enable_translation_i.eq(1)
  88     yield dut.asid_i.eq(1)
  89
  90     yield dut.itlb_access_i.eq(1)
  91     yield dut.itlb_hit_i.eq(0)
  92     yield dut.itlb_vaddr_i.eq(0x800000)
  93
  94     yield
  95     yield
  96     yield
  97
  98     yield dut.itlb_access_i.eq(1)
  99     yield dut.itlb_hit_i.eq(0)
 100     yield dut.itlb_vaddr_i.eq(0x200000)
 101
 102     yield
 103     yield
 104     yield
 105
 106     yield dut.req_port_i.data_gnt.eq(0)
 107     yield dut.itlb_access_i.eq(1)
 108     yield dut.itlb_hit_i.eq(0)
 109     yield dut.itlb_vaddr_i.eq(0x800011)
 110
 111     yield
 112     yield dut.req_port_i.data_gnt.eq(1)
 113     yield
 114     yield
 115
 116     yield
 117
 118
 119
 120 if __name__ == "__main__":
 121     dut = PTW()
 122     run_simulation(dut, testbench(dut), vcd_name="test_ptw.vcd")