1 from nmigen
.compat
.sim
import run_simulation
6 yield dut
.lu_vaddr_i
.eq(addr
)
7 yield dut
.update_i
.vpn
.eq(addr
>>12)
11 yield dut
.lu_access_i
.eq(1)
12 yield dut
.lu_asid_i
.eq(1)
13 yield dut
.update_i
.valid
.eq(1)
14 yield dut
.update_i
.is_1G
.eq(0)
15 yield dut
.update_i
.is_2M
.eq(0)
16 yield dut
.update_i
.asid
.eq(1)
17 yield dut
.update_i
.content
.ppn
.eq(0)
18 yield dut
.update_i
.content
.rsw
.eq(0)
19 yield dut
.update_i
.content
.r
.eq(1)
24 yield from set_vaddr(addr
)
28 yield from set_vaddr(addr
)
32 yield from set_vaddr(addr
)
36 yield from set_vaddr(addr
)
39 yield from set_vaddr(addr
)
43 yield from set_vaddr(addr
)
47 yield from set_vaddr(addr
)
50 yield dut
.update_i
.is_1G
.eq(1)
52 yield from set_vaddr(addr
)
55 yield dut
.update_i
.is_1G
.eq(1)
57 yield from set_vaddr(addr
)
63 if __name__
== "__main__":
65 run_simulation(dut
, testbench(dut
), vcd_name
="test_tlb.vcd")