src/TLB/test/test_tlb.py

   1 #import tracemalloc
   2 #tracemalloc.start()
   3
   4 from nmigen.compat.sim import run_simulation
   5
   6 from TLB.TLB import TLB
   7
   8 from TestUtil.test_helper import assert_op, assert_eq
   9
  10 #self.supermode = Signal(1) # Supervisor Mode
  11 #self.super_access = Signal(1) # Supervisor Access
  12 #self.command = Signal(2) # 00=None, 01=Search, 10=Write L1, 11=Write L2
  13 #self.xwr = Signal(3) # Execute, Write, Read
  14 #self.mode = Signal(4) # 4 bits for access to Sv48 on Rv64
  15 #self.address_L1 = Signal(max=L1_size)
  16 #self.asid = Signal(asid_size) # Address Space IDentifier (ASID)
  17 #self.vma = Signal(vma_size) # Virtual Memory Address (VMA)
  18 #self.pte_in = Signal(pte_size) # To be saved Page Table Entry (PTE)
  19 #
  20 #self.hit = Signal(1) # Denotes if the VMA had a mapped PTE
  21 #self.perm_valid = Signal(1) # Denotes if the permissions are correct
  22 #self.pte_out = Signal(pte_size) # PTE that was mapped to by the VMA
  23
  24 COMMAND_READ=1
  25 COMMAND_WRITE_L1=2
  26
  27 # Checks the data state of the CAM entry
  28 # Arguments:
  29 #   dut: The CamEntry being tested
  30 #   d (Data): The expected data
  31 #   op (Operation): (0 => ==), (1 => !=)
  32 def check_hit(dut, d):
  33     hit_d = yield dut.hit
  34     #assert_eq("hit", hit_d, d)
  35
  36 def test_command(dut,cmd,xwr,cycles):
  37     yield dut.command.eq(cmd)
  38     yield dut.xwr.eq(xwr)
  39     for i in range(0,cycles):
  40         yield
  41
  42 def test_write_L1(dut,vma,address_L1,asid,pte_in):
  43     yield dut.address_L1.eq(address_L1)
  44     yield dut.asid.eq(asid)
  45     yield dut.vma.eq(vma)
  46     yield dut.pte_in.eq(pte_in)
  47     yield from test_command(dut,COMMAND_WRITE_L1,7,2)
  48
  49 def test_search(dut,vma,found):
  50     yield dut.vma.eq(vma)
  51     yield from test_command(dut,COMMAND_READ,7,1)
  52     yield from check_hit(dut,found)
  53
  54 def zero(dut):
  55     yield dut.supermode.eq(0)
  56     yield dut.super_access.eq(0)
  57     yield dut.mode.eq(0)
  58     yield dut.address_L1.eq(0)
  59     yield dut.asid.eq(0)
  60     yield dut.vma.eq(0)
  61     yield dut.pte_in.eq(0)
  62
  63 def tbench(dut):
  64     yield from zero(dut)
  65     yield dut.mode.eq(0xF) # enable TLB
  66     #test hit
  67     yield from test_write_L1(dut,0xFEEDFACE,0,0xFFFF,0xF0F0)
  68     yield from test_search(dut,0xFEEDFACE,1)
  69     yield from test_search(dut,0xFACEFEED,0)
  70
  71
  72
  73
  74 def test_tlb():
  75     dut = TLB(15,36,64,8)
  76     run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
  77     print("TLB Unit Test Success")
  78
  79 if __name__ == "__main__":
  80     test_tlb()