src/TLB/test/test_tlb.py

   1 import tracemalloc
   2
   3 tracemalloc.start()
   4
   5 from nmigen.compat.sim import run_simulation
   6
   7 from TLB.TLB import TLB
   8
   9 from TestUtil.test_helper import assert_op
  10
  11 def tbench(dut):
  12     pass
  13
  14 def test_tlb():
  15     #FIXME UnusedElaboratable when the following line is uncommented
  16     #dut = TLB(15,36,64,8)
  17     #run_simulation(dut, tbench(dut), vcd_name="Waveforms/test_tlb.vcd")
  18     print("TLB Unit Test TODO")
  19
  20 if __name__ == "__main__":
  21     test_tlb()