src/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6
   7 """ Computation Unit (aka "ALU Manager").
   8
   9     This module runs a "revolving door" set of three latches, based on
  10     * Issue
  11     * Go_Read
  12     * Go_Write
  13     where one of them cannot be set on any given cycle.
  14     (Note however that opc_l has been inverted (and qn used), due to SRLatch
  15      default reset state being "0" rather than "1")
  16
  17     * When issue is first raised, a busy signal is sent out.
  18       The src1 and src2 registers and the operand can be latched in
  19       at this point
  20
  21     * Read request is set, which is acknowledged through the Scoreboard
  22       to the priority picker, which generates (one and only one) Go_Read
  23       at a time.  One of those will (eventually) be this Computation Unit.
  24
  25     * Once Go_Read is set, the src1/src2/operand latch door shuts (locking
  26       src1/src2/operand in place), and the ALU is told to proceed.
  27
  28     * As this is currently a "demo" unit, a countdown timer is activated
  29       to simulate an ALU "pipeline", which activates "write request release",
  30       and the ALU's output is captured into a temporary register.
  31
  32     * Write request release will go through a similar process as Read request,
  33       resulting (eventually) in Go_Write being asserted.
  34
  35     * When Go_Write is asserted, two things happen: (1) the data in the temp
  36       register is placed combinatorially onto the output, and (2) the
  37       req_l latch is cleared, busy is dropped, and the Comp Unit is back
  38       through its revolving door to do another task.
  39 """
  40
  41 class ComputationUnitNoDelay(Elaboratable):
  42     def __init__(self, rwid, opwid, alu):
  43         self.rwid = rwid
  44         self.alu = alu
  45
  46         self.counter = Signal(4)
  47         self.go_rd_i = Signal(reset_less=True) # go read in
  48         self.go_wr_i = Signal(reset_less=True) # go write in
  49         self.issue_i = Signal(reset_less=True) # fn issue in
  50         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  51         self.go_die_i = Signal() # go die (reset)
  52
  53         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  54         self.imm_i = Signal(rwid, reset_less=True) # immediate in
  55         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  56         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  57
  58         self.busy_o = Signal(reset_less=True) # fn busy out
  59         self.data_o = Signal(rwid, reset_less=True) # Dest out
  60         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
  61         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  62
  63     def elaborate(self, platform):
  64         m = Module()
  65         m.submodules.alu = self.alu
  66         m.submodules.src_l = src_l = SRLatch(sync=False)
  67         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  68         m.submodules.req_l = req_l = SRLatch(sync=False)
  69
  70         # shadow/go_die
  71         reset_w = Signal(reset_less=True)
  72         reset_r = Signal(reset_less=True)
  73         m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
  74         m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
  75
  76         # This is fascinating and very important to observe that this
  77         # is in effect a "3-way revolving door".  At no time may all 3
  78         # latches be set at the same time.
  79
  80         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
  81         m.d.sync += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
  82         m.d.sync += opc_l.r.eq(reset_w)      # XXX NOTE: INVERTED FROM book!
  83
  84         # src operand latch (not using go_wr_i)
  85         m.d.sync += src_l.s.eq(self.issue_i)
  86         m.d.sync += src_l.r.eq(reset_r)
  87
  88         # dest operand latch (not using issue_i)
  89         m.d.sync += req_l.s.eq(self.go_rd_i)
  90         m.d.sync += req_l.r.eq(reset_w)
  91
  92         # XXX
  93         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
  94         # XXX
  95
  96         # outputs
  97         busy_o = self.busy_o
  98         m.d.comb += busy_o.eq(opc_l.q) # busy out
  99         m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 100
 101         # the counter is just for demo purposes, to get the ALUs of different
 102         # types to take arbitrary completion times
 103         with m.If(opc_l.qn):
 104             m.d.sync += self.counter.eq(0)
 105         with m.If(req_l.qn & busy_o & (self.counter == 0)):
 106             with m.If(self.alu.op == 2): # MUL, to take 5 instructions
 107                 m.d.sync += self.counter.eq(5)
 108             with m.Elif(self.alu.op == 3): # SHIFT to take 7
 109                 m.d.sync += self.counter.eq(7)
 110             with m.Elif(self.alu.op >= 4): # Branches take 6 (to test shadow)
 111                 m.d.sync += self.counter.eq(6)
 112             with m.Else(): # ADD/SUB to take 2
 113                 m.d.sync += self.counter.eq(2)
 114         with m.If(self.counter > 1):
 115             m.d.sync += self.counter.eq(self.counter - 1)
 116         with m.If(self.counter == 1):
 117             # write req release out.  waits until shadow is dropped.
 118             m.d.comb += self.req_rel_o.eq(req_l.q & busy_o & self.shadown_i)
 119
 120         # create a latch/register for src1/src2
 121         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 122         latchregister(m, self.src2_i, self.alu.b, src_l.q)
 123         #with m.If(src_l.qn):
 124         #    m.d.comb += self.alu.op.eq(self.oper_i)
 125
 126         # create a latch/register for the operand
 127         latchregister(m, self.oper_i, self.alu.op, self.issue_i)
 128
 129         # and one for the output from the ALU
 130         data_r = Signal(self.rwid, reset_less=True) # Dest register
 131         latchregister(m, self.alu.o, data_r, req_l.q)
 132
 133         with m.If(self.go_wr_i):
 134             m.d.comb += self.data_o.eq(data_r)
 135
 136         return m
 137
 138 def scoreboard_sim(dut):
 139     yield dut.dest_i.eq(1)
 140     yield dut.issue_i.eq(1)
 141     yield
 142     yield dut.issue_i.eq(0)
 143     yield
 144     yield dut.src1_i.eq(1)
 145     yield dut.issue_i.eq(1)
 146     yield
 147     yield
 148     yield
 149     yield dut.issue_i.eq(0)
 150     yield
 151     yield dut.go_read_i.eq(1)
 152     yield
 153     yield dut.go_read_i.eq(0)
 154     yield
 155     yield dut.go_write_i.eq(1)
 156     yield
 157     yield dut.go_write_i.eq(0)
 158     yield
 159
 160 def test_scoreboard():
 161     dut = Scoreboard(32, 8)
 162     vl = rtlil.convert(dut, ports=dut.ports())
 163     with open("test_scoreboard.il", "w") as f:
 164         f.write(vl)
 165
 166     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 167
 168 if __name__ == '__main__':
 169     test_scoreboard()