src/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6
   7
   8 class ComputationUnitNoDelay(Elaboratable):
   9     def __init__(self, rwid, opwid, alu):
  10         self.rwid = rwid
  11         self.alu = alu
  12
  13         self.counter = Signal(3)
  14         self.go_rd_i = Signal(reset_less=True) # go read in
  15         self.go_wr_i = Signal(reset_less=True) # go write in
  16         self.issue_i = Signal(reset_less=True) # fn issue in
  17
  18         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  19         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  20         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  21
  22         self.busy_o = Signal(reset_less=True) # fn busy out
  23         self.data_o = Signal(rwid, reset_less=True) # Dest out
  24         self.rd_rel_o = Signal(reset_less=True) # release src1/src2 request
  25         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  26
  27     def elaborate(self, platform):
  28         m = Module()
  29         m.submodules.alu = self.alu
  30         m.submodules.src_l = src_l = SRLatch(sync=False)
  31         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  32         m.submodules.req_l = req_l = SRLatch(sync=False)
  33
  34         # This is fascinating and very important to observe that this
  35         # is in effect a "3-way revolving door".  At no time may all 3
  36         # latches be set at the same time.
  37
  38         # opcode latch (not using go_rd_i) - inverted so that busy resets to 0
  39         m.d.comb += opc_l.s.eq(self.issue_i) # XXX NOTE: INVERTED FROM book!
  40         m.d.comb += opc_l.r.eq(self.go_wr_i) # XXX NOTE: INVERTED FROM book!
  41
  42         # src operand latch (not using go_wr_i)
  43         m.d.comb += src_l.s.eq(self.issue_i)
  44         m.d.comb += src_l.r.eq(self.go_rd_i)
  45
  46         # dest operand latch (not using issue_i)
  47         m.d.comb += req_l.s.eq(self.go_rd_i)
  48         m.d.comb += req_l.r.eq(self.go_wr_i)
  49
  50         # XXX
  51         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
  52         # XXX
  53
  54         # outputs
  55         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
  56         m.d.comb += self.rd_rel_o.eq(src_l.q & opc_l.q) # src1/src2 req rel
  57
  58         with m.If(req_l.qn & opc_l.q & (self.counter == 0)):
  59             m.d.sync += self.counter.eq(3)
  60         with m.If(self.counter > 0):
  61             m.d.sync += self.counter.eq(self.counter - 1)
  62         with m.If((self.counter == 1) | (self.counter == 0)):
  63             m.d.comb += self.req_rel_o.eq(req_l.q & opc_l.q) # req release out
  64
  65         # create a latch/register for src1/src2
  66         latchregister(m, self.src1_i, self.alu.a, src_l.q)
  67         latchregister(m, self.src2_i, self.alu.b, src_l.q)
  68         #with m.If(src_l.qn):
  69         #    m.d.comb += self.alu.op.eq(self.oper_i)
  70
  71         # create a latch/register for the operand
  72         latchregister(m, self.oper_i, self.alu.op, src_l.q)
  73
  74         # and one for the output from the ALU
  75         data_o = Signal(self.rwid, reset_less=True) # Dest register
  76         latchregister(m, self.alu.o, data_o, req_l.q)
  77
  78         with m.If(self.go_wr_i):
  79             m.d.comb += self.data_o.eq(data_o)
  80
  81         return m
  82
  83 def scoreboard_sim(dut):
  84     yield dut.dest_i.eq(1)
  85     yield dut.issue_i.eq(1)
  86     yield
  87     yield dut.issue_i.eq(0)
  88     yield
  89     yield dut.src1_i.eq(1)
  90     yield dut.issue_i.eq(1)
  91     yield
  92     yield
  93     yield
  94     yield dut.issue_i.eq(0)
  95     yield
  96     yield dut.go_read_i.eq(1)
  97     yield
  98     yield dut.go_read_i.eq(0)
  99     yield
 100     yield dut.go_write_i.eq(1)
 101     yield
 102     yield dut.go_write_i.eq(0)
 103     yield
 104
 105 def test_scoreboard():
 106     dut = Scoreboard(32, 8)
 107     vl = rtlil.convert(dut, ports=dut.ports())
 108     with open("test_scoreboard.il", "w") as f:
 109         f.write(vl)
 110
 111     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
 112
 113 if __name__ == '__main__':
 114     test_scoreboard()