src/experiment/compalu.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable
   4
   5 from nmutil.latch import SRLatch
   6
   7
   8 class ComputationUnitNoDelay(Elaboratable):
   9     def __init__(self, rwid, opwid, alu):
  10         self.rwid = rwid
  11         self.alu = alu
  12
  13         self.go_rd_i = Signal(reset_less=True) # go read in
  14         self.go_wr_i = Signal(reset_less=True) # go write in
  15         self.issue_i = Signal(reset_less=True) # fn issue in
  16
  17         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  18         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  19         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  20
  21         self.busy_o = Signal(reset_less=True) # fn busy out
  22         self.data_o = Signal(rwid, reset_less=True) # Dest out
  23         self.req_rel_o = Signal(reset_less=True) # release request out (valid_o)
  24
  25     def elaborate(self, platform):
  26         m = Module()
  27         m.submodules.alu = self.alu
  28         m.submodules.src_l = src_l = SRLatch(sync=False)
  29         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  30         m.submodules.req_l = req_l = SRLatch(sync=False)
  31
  32         # This is fascinating and very important to observe that this
  33         # is in effect a "3-way revolving door".  At no time may all 3
  34         # latches be set at the same time.
  35
  36         # opcode latch (not using go_rd_i)
  37         m.d.comb += opc_l.s.eq(self.go_wr_i)
  38         m.d.comb += opc_l.r.eq(self.issue_i)
  39
  40         # src operand latch (not using go_wr_i)
  41         m.d.comb += src_l.s.eq(self.issue_i)
  42         m.d.comb += src_l.r.eq(self.go_rd_i)
  43
  44         # dest operand latch (not using issue_i)
  45         m.d.comb += req_l.s.eq(self.go_rd_i)
  46         m.d.comb += req_l.r.eq(self.go_wr_i)
  47
  48         # XXX
  49         # XXX NOTE: sync on req_rel_o and data_o due to simulation lock-up
  50         # XXX
  51
  52         # outputs
  53         m.d.comb += self.busy_o.eq(opc_l.qn) # busy out
  54         m.d.comb += self.req_rel_o.eq(req_l.qn & opc_l.q) # request release out
  55
  56         with m.If(src_l.q):
  57             m.d.comb += self.alu.a.eq(self.src1_i)
  58             m.d.comb += self.alu.b.eq(self.src2_i)
  59
  60         #with m.If(opc_l.q): # XXX operand type in at same time as src1/src2
  61             m.d.comb += self.alu.op.eq(self.oper_i)
  62
  63         with m.If(req_l.qn):
  64             m.d.comb += self.data_o.eq(self.alu.o)
  65
  66         return m
  67
  68 def scoreboard_sim(dut):
  69     yield dut.dest_i.eq(1)
  70     yield dut.issue_i.eq(1)
  71     yield
  72     yield dut.issue_i.eq(0)
  73     yield
  74     yield dut.src1_i.eq(1)
  75     yield dut.issue_i.eq(1)
  76     yield
  77     yield
  78     yield
  79     yield dut.issue_i.eq(0)
  80     yield
  81     yield dut.go_read_i.eq(1)
  82     yield
  83     yield dut.go_read_i.eq(0)
  84     yield
  85     yield dut.go_write_i.eq(1)
  86     yield
  87     yield dut.go_write_i.eq(0)
  88     yield
  89
  90 def test_scoreboard():
  91     dut = Scoreboard(32, 8)
  92     vl = rtlil.convert(dut, ports=dut.ports())
  93     with open("test_scoreboard.il", "w") as f:
  94         f.write(vl)
  95
  96     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_scoreboard.vcd')
  97
  98 if __name__ == '__main__':
  99     test_scoreboard()