src/experiment/compldst.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Cat, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6
   7 """ LOAD / STORE Computation Unit.  Also capable of doing ADD and ADD immediate
   8
   9     This module runs a "revolving door" set of four latches, based on
  10     * Issue
  11     * Go_Read
  12     * Go_Addr
  13     * Go_Write *OR* Go_Store
  14
  15     (Note that opc_l has been inverted (and qn used), due to SRLatch
  16      default reset state being "0" rather than "1")
  17 """
  18
  19 # internal opcodes.  hypothetically this could do more combinations.
  20 # meanings:
  21 # * bit 0: 0 = ADD , 1 = SUB
  22 # * bit 1: 0 = src1, 1 = IMM
  23 # * bit 2: 1 = LD
  24 # * bit 3: 1 = ST
  25 LDST_OP_ADDI = 0b0000 # plain ADD (src1 + src2)
  26 LDST_OP_SUBI = 0b0001 # plain SUB (src1 - src2)
  27 LDST_OP_ADD  = 0b0010 # immed ADD (imm + src1)
  28 LDST_OP_SUB  = 0b0011 # immed SUB (imm - src1)
  29 LDST_OP_ST   = 0b0110 # immed ADD plus LD op.  ADD result is address
  30 LDST_OP_LD   = 0b1010 # immed ADD plus ST op.  ADD result is address
  31
  32
  33 class LDSTCompUnit(Elaboratable):
  34     """ LOAD / STORE / ADD / SUB Computation Unit
  35
  36         Inputs
  37         ------
  38
  39         * :rwid:   register width
  40         * :alu:    an ALU module
  41         * :mem:    a Memory Module (read-write capable)
  42
  43         Control Signals (In)
  44         --------------------
  45
  46         * :issue_i:    LD/ST is being "issued".
  47         * :isalu_i:    ADD/SUB is being "issued" (aka issue_alu_i)
  48         * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
  49         * :go_rd_i:    read is being actioned (latches in src regs)
  50         * :go_ad_i:    address is being actioned (triggers actual mem LD)
  51         * :go_st_i:    store is being actioned (triggers actual mem STORE)
  52         * :go_die_i:   resets the unit back to "wait for issue"
  53     """
  54     def __init__(self, rwid, opwid, alu, mem):
  55         self.opwid = opwid
  56         self.rwid = rwid
  57         self.alu = alu
  58         self.mem = mem
  59
  60         self.counter = Signal(4)
  61         self.go_rd_i = Signal(reset_less=True) # go read in
  62         self.go_ad_i = Signal(reset_less=True) # go address in
  63         self.go_wr_i = Signal(reset_less=True) # go write in
  64         self.go_st_i = Signal(reset_less=True) # go store in
  65         self.issue_i = Signal(reset_less=True) # fn issue in
  66         self.isalu_i = Signal(reset_less=True) # fn issue as ALU in
  67         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  68         self.go_die_i = Signal() # go die (reset)
  69
  70         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  71         self.imm_i = Signal(rwid, reset_less=True) # immediate in
  72         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  73         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  74
  75         self.busy_o = Signal(reset_less=True)       # fn busy out
  76         self.rd_rel_o = Signal(reset_less=True) # request src1/src2
  77         self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
  78         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
  79         self.req_rel_o = Signal(reset_less=True) # request write (result)
  80         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
  81         self.addr_o = Signal(rwid, reset_less=True) # Address out (LD or ST)
  82
  83         # hmm... TODO... move these to outside of LDSTCompUnit
  84         self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
  85         self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
  86         self.ld_o = Signal(reset_less=True) # operation is a LD
  87         self.st_o = Signal(reset_less=True) # operation is a ST
  88
  89     def elaborate(self, platform):
  90         m = Module()
  91         comb = m.d.comb
  92         sync = m.d.sync
  93
  94         m.submodules.alu = self.alu
  95         m.submodules.src_l = src_l = SRLatch(sync=False)
  96         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  97         m.submodules.adr_l = adr_l = SRLatch(sync=False)
  98         m.submodules.req_l = req_l = SRLatch(sync=False)
  99         m.submodules.sto_l = sto_l = SRLatch(sync=False)
 100
 101         # shadow/go_die
 102         reset_b = Signal(reset_less=True)
 103         reset_w = Signal(reset_less=True)
 104         reset_a = Signal(reset_less=True)
 105         reset_s = Signal(reset_less=True)
 106         reset_r = Signal(reset_less=True)
 107         comb += reset_b.eq(self.go_st_i | self.go_wr_i | self.go_die_i)
 108         comb += reset_w.eq(self.go_wr_i | self.go_die_i)
 109         comb += reset_s.eq(self.go_st_i | self.go_die_i)
 110         comb += reset_r.eq(self.go_rd_i | self.go_die_i)
 111         # this one is slightly different, issue_alu_i selects go_wr_i)
 112         a_sel = Mux(self.isalu_i, self.go_wr_i, self.go_ad_i)
 113         comb += reset_a.eq(a_sel| self.go_die_i)
 114
 115         # opcode decode
 116         op_alu = Signal(reset_less=True)
 117         op_is_ld = Signal(reset_less=True)
 118         op_is_st = Signal(reset_less=True)
 119         op_ldst = Signal(reset_less=True)
 120         op_is_imm = Signal(reset_less=True)
 121
 122         # select immediate or src2 reg to add
 123         src2_or_imm = Signal(self.rwid, reset_less=True)
 124         src_sel = Signal(reset_less=True)
 125
 126         # issue can be either issue_i or issue_alu_i (isalu_i)
 127         issue_i = Signal(reset_less=True)
 128         comb += issue_i.eq(self.issue_i | self.isalu_i)
 129
 130         # Ripple-down the latches, each one set cancels the previous.
 131         # NOTE: use sync to stop combinatorial loops.
 132
 133         # opcode latch - inverted so that busy resets to 0
 134         sync += opc_l.s.eq(issue_i) # XXX NOTE: INVERTED FROM book!
 135         sync += opc_l.r.eq(reset_b) # XXX NOTE: INVERTED FROM book!
 136
 137         # src operand latch
 138         sync += src_l.s.eq(issue_i)
 139         sync += src_l.r.eq(reset_r)
 140
 141         # addr latch
 142         sync += adr_l.s.eq(self.go_rd_i)
 143         sync += adr_l.r.eq(reset_a)
 144
 145         # dest operand latch
 146         sync += req_l.s.eq(self.go_ad_i)
 147         sync += req_l.r.eq(reset_w)
 148
 149         # store latch
 150         sync += sto_l.s.eq(self.go_ad_i)
 151         sync += sto_l.r.eq(reset_s)
 152
 153         # outputs: busy and release signals
 154         busy_o = self.busy_o
 155         comb += self.busy_o.eq(opc_l.q) # busy out
 156         comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 157         comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i & op_is_st)
 158
 159         # request release enabled based on if op is a LD/ST or a plain ALU
 160         # if op is an ADD/SUB or a LD, req_rel activates.
 161         wr_q = Signal(reset_less=True)
 162         comb += wr_q.eq(req_l.q & (~op_ldst | op_is_ld))
 163
 164         alulatch = Signal(reset_less=True)
 165         comb += alulatch.eq((op_ldst & self.adr_rel_o) | \
 166                             (~op_ldst & self.req_rel_o))
 167
 168         # only proceed if ALU says its output is valid
 169         with m.If(self.alu.n_valid_o):
 170
 171             # write req release out.  waits until shadow is dropped.
 172             comb += self.req_rel_o.eq(wr_q & busy_o & self.shadown_i)
 173             # address release only happens on LD/ST, and is shadowed.
 174             comb += self.adr_rel_o.eq(adr_l.q & op_ldst & busy_o & \
 175                                       self.shadown_i)
 176             # when output latch is ready, and ALU says ready, accept ALU output
 177             with m.If(self.req_rel_o):
 178                 m.d.comb += self.alu.n_ready_i.eq(1) # tells ALU "thanks got it"
 179
 180         # select immediate if opcode says so.  however also change the latch
 181         # to trigger *from* the opcode latch instead.
 182         comb += src_sel.eq(Mux(op_is_imm, opc_l.qn, src_l.q))
 183         comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i, self.src2_i))
 184
 185         # create a latch/register for src1/src2 (include immediate select)
 186         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 187         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 188
 189         # create a latch/register for the operand
 190         oper_r = Signal(self.opwid, reset_less=True) # Dest register
 191         latchregister(m, self.oper_i, oper_r, self.issue_i)
 192         alu_op = Cat(op_alu, 0, op_is_imm) # using alu_hier, here.
 193         comb += self.alu.op.eq(alu_op)
 194
 195         # and one for the output from the ALU
 196         data_r = Signal(self.rwid, reset_less=True) # Dest register
 197         latchregister(m, self.alu.o, data_r, alulatch)
 198
 199         # decode bits of operand (latched)
 200         comb += op_alu.eq(oper_r[0])
 201         comb += op_is_imm.eq(oper_r[1])
 202         comb += op_is_ld.eq(oper_r[2])
 203         comb += op_is_st.eq(oper_r[3])
 204         comb += op_ldst.eq(op_is_ld | op_is_st)
 205         comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 206         comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 207         comb += self.ld_o.eq(op_is_ld)
 208         comb += self.st_o.eq(op_is_st)
 209
 210         # on a go_read, tell the ALU we're accepting data.
 211         # NOTE: this spells TROUBLE if the ALU isn't ready!
 212         # go_read is only valid for one clock!
 213         with m.If(self.go_rd_i):                     # src operands ready, GO!
 214             with m.If(~self.alu.p_ready_o):          # no ACK yet
 215                 m.d.comb += self.alu.p_valid_i.eq(1) # so indicate valid
 216
 217         # put the register directly onto the output
 218         with m.If((self.go_wr_i & ~op_ldst) | (self.go_st_i & op_is_st)):
 219             comb += self.data_o.eq(data_r)
 220
 221         # put the register directly onto the address bus
 222         with m.If(self.go_ad_i):
 223             comb += self.addr_o.eq(data_r)
 224
 225         return m
 226
 227     def __iter__(self):
 228         yield self.go_rd_i
 229         yield self.go_ad_i
 230         yield self.go_wr_i
 231         yield self.go_st_i
 232         yield self.issue_i
 233         yield self.isalu_i
 234         yield self.shadown_i
 235         yield self.go_die_i
 236         yield self.oper_i
 237         yield self.imm_i
 238         yield self.src1_i
 239         yield self.src2_i
 240         yield self.busy_o
 241         yield self.rd_rel_o
 242         yield self.adr_rel_o
 243         yield self.sto_rel_o
 244         yield self.req_rel_o
 245         yield self.data_o
 246         yield self.load_mem_o
 247         yield self.stwd_mem_o
 248
 249     def ports(self):
 250         return list(self)
 251
 252
 253 def scoreboard_sim(dut):
 254     yield dut.dest_i.eq(1)
 255     yield dut.issue_i.eq(1)
 256     yield
 257     yield dut.issue_i.eq(0)
 258     yield
 259     yield dut.src1_i.eq(1)
 260     yield dut.issue_i.eq(1)
 261     yield
 262     yield
 263     yield
 264     yield dut.issue_i.eq(0)
 265     yield
 266     yield dut.go_read_i.eq(1)
 267     yield
 268     yield dut.go_read_i.eq(0)
 269     yield
 270     yield dut.go_write_i.eq(1)
 271     yield
 272     yield dut.go_write_i.eq(0)
 273     yield
 274
 275
 276 def test_scoreboard():
 277     from alu_hier import ALU
 278     alu = ALU(16)
 279     mem = alu # fake
 280     dut = LDSTCompUnit(16, 4, alu, mem)
 281     vl = rtlil.convert(dut, ports=dut.ports())
 282     with open("test_ldst_comp.il", "w") as f:
 283         f.write(vl)
 284
 285     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 286
 287 if __name__ == '__main__':
 288     test_scoreboard()