src/experiment/compldst.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Mux, Cat, Elaboratable
   4
   5 from nmutil.latch import SRLatch, latchregister
   6
   7 """ LOAD / STORE Computation Unit.  Also capable of doing ADD and ADD immediate
   8
   9     This module runs a "revolving door" set of four latches, based on
  10     * Issue
  11     * Go_Read
  12     * Go_Addr
  13     * Go_Write *OR* Go_Store
  14
  15     (Note that opc_l has been inverted (and qn used), due to SRLatch
  16      default reset state being "0" rather than "1")
  17 """
  18
  19 # internal opcodes.  hypothetically this could do more combinations.
  20 # meanings:
  21 # * bit 0: 0 = ADD , 1 = SUB
  22 # * bit 1: 0 = src1, 1 = IMM
  23 # * bit 2: 1 = LD
  24 # * bit 3: 1 = ST
  25 LDST_OP_ADDI = 0b0000 # plain ADD (src1 + src2)
  26 LDST_OP_SUBI = 0b0001 # plain SUB (src1 - src2)
  27 LDST_OP_ADD  = 0b0010 # immed ADD (imm + src1)
  28 LDST_OP_SUB  = 0b0011 # immed SUB (imm - src1)
  29 LDST_OP_ST   = 0b0110 # immed ADD plus LD op.  ADD result is address
  30 LDST_OP_LD   = 0b1010 # immed ADD plus ST op.  ADD result is address
  31
  32
  33 class LDSTCompUnit(Elaboratable):
  34     """ LOAD / STORE / ADD / SUB Computation Unit
  35
  36         Inputs
  37         ------
  38
  39         * :rwid:   register width
  40         * :alu:    an ALU module
  41         * :mem:    a Memory Module (read-write capable)
  42
  43         Control Signals (In)
  44         --------------------
  45
  46         * :issue_i:    LD/ST is being "issued".
  47         * :isalu_i:    ADD/SUB is being "issued" (aka issue_alu_i)
  48         * :shadown_i:  Inverted-shadow is being held (stops STORE *and* WRITE)
  49         * :go_rd_i:    read is being actioned (latches in src regs)
  50         * :go_ad_i:    address is being actioned (triggers actual mem LD)
  51         * :go_st_i:    store is being actioned (triggers actual mem STORE)
  52         * :go_die_i:   resets the unit back to "wait for issue"
  53     """
  54     def __init__(self, rwid, opwid, alu, mem):
  55         self.rwid = rwid
  56         self.alu = alu
  57         self.mem = mem
  58
  59         self.counter = Signal(4)
  60         self.go_rd_i = Signal(reset_less=True) # go read in
  61         self.go_ad_i = Signal(reset_less=True) # go address in
  62         self.go_wr_i = Signal(reset_less=True) # go write in
  63         self.go_st_i = Signal(reset_less=True) # go store in
  64         self.issue_i = Signal(reset_less=True) # fn issue in
  65         self.isalu_i = Signal(reset_less=True) # fn issue as ALU in
  66         self.shadown_i = Signal(reset=1) # shadow function, defaults to ON
  67         self.go_die_i = Signal() # go die (reset)
  68
  69         self.oper_i = Signal(opwid, reset_less=True) # opcode in
  70         self.imm_i = Signal(rwid, reset_less=True) # immediate in
  71         self.src1_i = Signal(rwid, reset_less=True) # oper1 in
  72         self.src2_i = Signal(rwid, reset_less=True) # oper2 in
  73
  74         self.busy_o = Signal(reset_less=True)       # fn busy out
  75         self.rd_rel_o = Signal(reset_less=True) # request src1/src2
  76         self.adr_rel_o = Signal(reset_less=True) # request address (from mem)
  77         self.sto_rel_o = Signal(reset_less=True) # request store (to mem)
  78         self.req_rel_o = Signal(reset_less=True) # request write (result)
  79         self.data_o = Signal(rwid, reset_less=True) # Dest out (LD or ALU)
  80         self.load_mem_o = Signal(reset_less=True) # activate memory LOAD
  81         self.stwd_mem_o = Signal(reset_less=True) # activate memory STORE
  82
  83     def elaborate(self, platform):
  84         m = Module()
  85         m.submodules.alu = self.alu
  86         m.submodules.src_l = src_l = SRLatch(sync=False)
  87         m.submodules.opc_l = opc_l = SRLatch(sync=False)
  88         m.submodules.adr_l = adr_l = SRLatch(sync=False)
  89         m.submodules.req_l = req_l = SRLatch(sync=False)
  90         m.submodules.sto_l = sto_l = SRLatch(sync=False)
  91
  92         # shadow/go_die
  93         reset_b = Signal(reset_less=True)
  94         reset_w = Signal(reset_less=True)
  95         reset_a = Signal(reset_less=True)
  96         reset_s = Signal(reset_less=True)
  97         reset_r = Signal(reset_less=True)
  98         m.d.comb += reset_b.eq(self.go_st_i | self.go_wr_i | self.go_die_i)
  99         m.d.comb += reset_w.eq(self.go_wr_i | self.go_die_i)
 100         m.d.comb += reset_s.eq(self.go_st_i | self.go_die_i)
 101         m.d.comb += reset_r.eq(self.go_rd_i | self.go_die_i)
 102         # this one is slightly different, issue_alu_i selects go_wr_i)
 103         a_sel = Mux(self.isalu_i, self.go_wr_i, self.go_ad_i )
 104         m.d.comb += reset_a.eq(a_sel| self.go_die_i)
 105
 106         # opcode decode
 107         op_alu = Signal(reset_less=True)
 108         op_is_ld = Signal(reset_less=True)
 109         op_is_st = Signal(reset_less=True)
 110         op_ldst = Signal(reset_less=True)
 111         op_is_imm = Signal(reset_less=True)
 112
 113         m.d.comb += op_alu.eq(self.oper_i[0])
 114         m.d.comb += op_is_imm.eq(self.oper_i[1])
 115         m.d.comb += op_is_ld.eq(self.oper_i[2])
 116         m.d.comb += op_is_st.eq(self.oper_i[3])
 117         m.d.comb += op_ldst.eq(op_is_ld | op_is_st)
 118         m.d.comb += self.load_mem_o.eq(op_is_ld & self.go_ad_i)
 119         m.d.comb += self.stwd_mem_o.eq(op_is_st & self.go_st_i)
 120
 121         # select immediate or src2 reg to add
 122         src2_or_imm = Signal(self.rwid, reset_less=True)
 123         src_sel = Signal(reset_less=True)
 124
 125         # issue can be either issue_i or issue_alu_i (isalu_i)
 126         issue_i = Signal(reset_less=True)
 127         m.d.comb += issue_i.eq(self.issue_i | self.isalu_i)
 128
 129         # Ripple-down the latches, each one set cancels the previous.
 130         # NOTE: use sync to stop combinatorial loops.
 131
 132         # opcode latch - inverted so that busy resets to 0
 133         m.d.sync += opc_l.s.eq(issue_i) # XXX NOTE: INVERTED FROM book!
 134         m.d.sync += opc_l.r.eq(reset_b) # XXX NOTE: INVERTED FROM book!
 135
 136         # src operand latch
 137         m.d.sync += src_l.s.eq(issue_i)
 138         m.d.sync += src_l.r.eq(reset_r)
 139
 140         # addr latch
 141         m.d.sync += adr_l.s.eq(self.go_rd_i)
 142         m.d.sync += adr_l.r.eq(reset_a)
 143
 144         # dest operand latch
 145         m.d.sync += req_l.s.eq(self.go_ad_i)
 146         m.d.sync += req_l.r.eq(reset_w)
 147
 148         # store latch
 149         m.d.sync += sto_l.s.eq(self.go_ad_i)
 150         m.d.sync += sto_l.r.eq(reset_s)
 151
 152         # outputs
 153         busy_o = self.busy_o
 154         m.d.comb += self.busy_o.eq(opc_l.q) # busy out
 155         m.d.comb += self.rd_rel_o.eq(src_l.q & busy_o) # src1/src2 req rel
 156         m.d.comb += self.adr_rel_o.eq(adr_l.q & ~op_ldst & busy_o)
 157         m.d.comb += self.sto_rel_o.eq(sto_l.q & busy_o & self.shadown_i)
 158
 159         # request release enabled based on if op is a LD/ST or a plain ALU
 160         # if op is a LD/ST, req_rel activates from the *address* latch
 161         # if op is ADD/SUB, req_rel activates from the *dest* latch
 162         wr_q = Signal(reset_less=True)
 163         m.d.comb += wr_q.eq(Mux(op_ldst, adr_l.q, req_l.q))
 164
 165         # the counter is just for demo purposes, to get the ALUs of different
 166         # types to take arbitrary completion times
 167         with m.If(opc_l.qn):
 168             m.d.sync += self.counter.eq(0) # reset counter when not busy
 169         with m.If(req_l.qn & busy_o & (self.counter == 0)):
 170             with m.If(self.oper_i == 2): # MUL, to take 5 instructions
 171                 m.d.sync += self.counter.eq(5)
 172             with m.Elif(self.oper_i == 3): # SHIFT to take 7
 173                 m.d.sync += self.counter.eq(7)
 174             with m.Else(): # ADD/SUB to take 2
 175                 m.d.sync += self.counter.eq(2)
 176         with m.If(self.counter > 1):
 177             m.d.sync += self.counter.eq(self.counter - 1)
 178         with m.If(self.counter == 1):
 179             # write req release out.  waits until shadow is dropped.
 180             m.d.comb += self.req_rel_o.eq(wr_q & busy_o & self.shadown_i)
 181
 182         # select immediate if opcode says so.  however also change the latch
 183         # to trigger *from* the opcode latch instead.
 184         m.d.comb += src_sel.eq(Mux(op_is_imm, opc_l.qn, src_l.q))
 185         m.d.comb += src2_or_imm.eq(Mux(op_is_imm, self.imm_i, self.src2_i))
 186
 187         # create a latch/register for src1/src2 (include immediate select)
 188         latchregister(m, self.src1_i, self.alu.a, src_l.q)
 189         latchregister(m, src2_or_imm, self.alu.b, src_sel)
 190
 191         # create a latch/register for the operand
 192         latchregister(m, Cat(op_alu, 0), self.alu.op, self.issue_i)
 193
 194         # and one for the output from the ALU
 195         data_r = Signal(self.rwid, reset_less=True) # Dest register
 196         latchregister(m, self.alu.o, data_r, req_l.q)
 197
 198         with m.If(self.go_wr_i):
 199             m.d.comb += self.data_o.eq(data_r)
 200
 201         return m
 202
 203     def __iter__(self):
 204         yield self.go_rd_i
 205         yield self.go_ad_i
 206         yield self.go_wr_i
 207         yield self.go_st_i
 208         yield self.issue_i
 209         yield self.isalu_i
 210         yield self.shadown_i
 211         yield self.go_die_i
 212         yield self.oper_i
 213         yield self.imm_i
 214         yield self.src1_i
 215         yield self.src2_i
 216         yield self.busy_o
 217         yield self.rd_rel_o
 218         yield self.adr_rel_o
 219         yield self.sto_rel_o
 220         yield self.req_rel_o
 221         yield self.data_o
 222         yield self.load_mem_o
 223         yield self.stwd_mem_o
 224
 225     def ports(self):
 226         return list(self)
 227
 228
 229 def scoreboard_sim(dut):
 230     yield dut.dest_i.eq(1)
 231     yield dut.issue_i.eq(1)
 232     yield
 233     yield dut.issue_i.eq(0)
 234     yield
 235     yield dut.src1_i.eq(1)
 236     yield dut.issue_i.eq(1)
 237     yield
 238     yield
 239     yield
 240     yield dut.issue_i.eq(0)
 241     yield
 242     yield dut.go_read_i.eq(1)
 243     yield
 244     yield dut.go_read_i.eq(0)
 245     yield
 246     yield dut.go_write_i.eq(1)
 247     yield
 248     yield dut.go_write_i.eq(0)
 249     yield
 250
 251
 252 def test_scoreboard():
 253     from alu_hier import ALU
 254     alu = ALU(16)
 255     mem = alu # fake
 256     dut = LDSTCompUnit(16, 4, alu, mem)
 257     vl = rtlil.convert(dut, ports=dut.ports())
 258     with open("test_ldst_comp.il", "w") as f:
 259         f.write(vl)
 260
 261     run_simulation(dut, scoreboard_sim(dut), vcd_name='test_ldst_comp.vcd')
 262
 263 if __name__ == '__main__':
 264     test_scoreboard()