src/experiment/score6600.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18 from random import randint
  19
  20
  21 class Scoreboard(Elaboratable):
  22     def __init__(self, rwid, n_regs):
  23         """ Inputs:
  24
  25             * :rwid:   bit width of register file(s) - both FP and INT
  26             * :n_regs: depth of register file(s) - number of FP and INT regs
  27         """
  28         self.rwid = rwid
  29         self.n_regs = n_regs
  30
  31         # Register Files
  32         self.intregs = RegFileArray(rwid, n_regs)
  33         self.fpregs = RegFileArray(rwid, n_regs)
  34
  35         # inputs
  36         self.int_store_i = Signal(reset_less=True) # instruction is a store
  37         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  38         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  39         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  40
  41         self.issue_o = Signal(reset_less=True) # instruction was accepted
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45
  46         m.submodules.intregs = self.intregs
  47         m.submodules.fpregs = self.fpregs
  48
  49         # register ports
  50         int_dest = self.intregs.write_port("dest")
  51         int_src1 = self.intregs.read_port("src1")
  52         int_src2 = self.intregs.read_port("src2")
  53
  54         fp_dest = self.fpregs.write_port("dest")
  55         fp_src1 = self.fpregs.read_port("src1")
  56         fp_src2 = self.fpregs.read_port("src2")
  57
  58         # Int ALUs
  59         add = ALU(self.rwid)
  60         sub = ALU(self.rwid)
  61         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  62         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  63         int_alus = [comp1, comp2]
  64
  65         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  66         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  67
  68         # Count of number of FUs
  69         n_int_fus = len(int_alus)
  70         n_fp_fus = 0 # for now
  71
  72         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  73
  74         # Integer FU-FU Dep Matrix
  75         intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  76         m.submodules.intfudeps = intfudeps
  77         # Integer FU-Reg Dep Matrix
  78         intregdeps = FURegDepMatrix(self.n_regs, n_int_fus)
  79         m.submodules.intregdeps = intregdeps
  80
  81         # Integer Priority Picker 1: Adder + Subtractor
  82         intpick1 = GroupPicker(2) # picks between add and sub
  83         m.submodules.intpick1 = intpick1
  84
  85         # Global Pending Vectors (INT and TODO FP)
  86         g_int_src1_pend_v = intregdeps.rd_src2_pend_o
  87         g_int_src2_pend_v = intregdeps.rd_src1_pend_o
  88         g_int_rd_pend_v = intregdeps.rd_pend_o
  89         g_int_wr_pend_v = intregdeps.wr_pend_o
  90
  91         # INT/FP Issue Unit
  92         regdecode = RegDecode(self.n_regs)
  93         m.submodules.regdecode = regdecode
  94         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
  95         m.submodules.issueunit = issueunit
  96
  97         #---------
  98         # ok start wiring things together...
  99         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 100         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 101         #---------
 102
 103         #---------
 104         # Issue Unit is where it starts.  set up some in/outs for this module
 105         #---------
 106         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 107                      regdecode.dest_i.eq(self.int_dest_i),
 108                      regdecode.src1_i.eq(self.int_src1_i),
 109                      regdecode.src2_i.eq(self.int_src2_i),
 110                      regdecode.enable_i.eq(1),
 111                      issueunit.i.dest_i.eq(regdecode.dest_o),
 112                      self.issue_o.eq(issueunit.issue_o)
 113                     ]
 114         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 115
 116         # connect global rd/wr pending vectors
 117         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v)
 118         # TODO: issueunit.f (FP)
 119
 120         # and int function issue / busy arrays, and dest/src1/src2
 121         fn_busy_l = []
 122         fn_issue_l = []
 123         for i, alu in enumerate(int_alus):
 124             fn_busy_l.append(alu.busy_o)
 125             fn_issue_l.append(issueunit.i.fn_issue_o[i])
 126
 127             m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 128             # XXX sync, so as to stop a simulation infinite loop
 129             m.d.comb += issueunit.i.busy_i[i].eq(alu.busy_o)
 130             #m.d.comb += alu.dest_i.eq(issueunit.i.dest_i)
 131             #m.d.comb += alu.src1_i.eq(issueunit.i.src1_i)
 132             #m.d.comb += alu.src2_i.eq(issueunit.i.src2_i)
 133             # NOTE: req_rel_o connected to picker, below.
 134
 135         fn_issue_o = Signal(len(fn_issue_l), reset_less=True)
 136         m.d.comb += fn_issue_o.eq(Cat(*fn_issue_l))
 137         #---------
 138         # connect fu-fu matrix
 139         #---------
 140
 141         m.d.comb += intfudeps.rd_pend_i.eq(g_int_rd_pend_v)
 142         m.d.comb += intfudeps.wr_pend_i.eq(g_int_wr_pend_v)
 143
 144         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 145         go_rd_i = intfudeps.go_rd_i
 146         go_wr_i = intfudeps.go_wr_i
 147         m.d.comb += go_rd_i[0].eq(intpick1.go_rd_o[0]) # add rd
 148         m.d.comb += go_wr_i[0].eq(intpick1.go_wr_o[0]) # add wr
 149
 150         m.d.comb += go_rd_i[1].eq(intpick1.go_rd_o[1]) # sub rd
 151         m.d.comb += go_wr_i[1].eq(intpick1.go_wr_o[1]) # sub wr
 152
 153         m.d.comb += intfudeps.issue_i.eq(fn_issue_o)
 154
 155         #---------
 156         # connect fu-dep matrix
 157         #---------
 158         r_go_rd_i = intregdeps.go_rd_i
 159         r_go_wr_i = intregdeps.go_wr_i
 160         m.d.comb += r_go_rd_i.eq(go_rd_i)
 161         m.d.comb += r_go_wr_i.eq(go_wr_i)
 162
 163         m.d.comb += intregdeps.dest_i.eq(regdecode.dest_o)
 164         m.d.comb += intregdeps.src1_i.eq(regdecode.src1_o)
 165         m.d.comb += intregdeps.src2_i.eq(regdecode.src2_o)
 166         m.d.comb += intregdeps.issue_i.eq(fn_issue_o)
 167
 168         # Connect Picker
 169         #---------
 170         m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
 171         m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
 172         int_readable_o = intfudeps.readable_o
 173         int_writable_o = intfudeps.writable_o
 174         m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
 175         m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
 176         m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
 177         m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
 178
 179         #---------
 180         # Connect Register File(s)
 181         #---------
 182         m.d.sync += int_dest.wen.eq(intregdeps.dest_rsel_o)
 183         m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
 184         m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
 185
 186         # merge (OR) all integer FU / ALU outputs to a single value
 187         # bit of a hack: treereduce needs a list with an item named "dest_o"
 188         dest_o = treereduce(int_alus)
 189         m.d.comb += int_dest.data_i.eq(dest_o)
 190
 191         # connect ALUs
 192         for i, alu in enumerate(int_alus):
 193             m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i])
 194             m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
 195             #m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 196             #m.d.comb += fn_busy_l[i].eq(alu.busy_o)  # XXX ignore, use fnissue
 197             m.d.comb += alu.src1_i.eq(int_src1.data_o)
 198             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 199
 200         return m
 201
 202
 203     def __iter__(self):
 204         yield from self.intregs
 205         yield from self.fpregs
 206         yield self.int_store_i
 207         yield self.int_dest_i
 208         yield self.int_src1_i
 209         yield self.int_src2_i
 210         yield self.issue_o
 211         #yield from self.int_src1
 212         #yield from self.int_dest
 213         #yield from self.int_src1
 214         #yield from self.int_src2
 215         #yield from self.fp_dest
 216         #yield from self.fp_src1
 217         #yield from self.fp_src2
 218
 219     def ports(self):
 220         return list(self)
 221
 222 IADD = 0
 223 ISUB = 1
 224
 225 class RegSim:
 226     def __init__(self, rwidth, nregs):
 227         self.rwidth = rwidth
 228         self.regs = [0] * nregs
 229
 230     def op(self, op, src1, src2, dest):
 231         src1 = self.regs[src1]
 232         src2 = self.regs[src2]
 233         if op == IADD:
 234             val = (src1 + src2) & ((1<<(self.rwidth))-1)
 235         elif op == ISUB:
 236             val = (src1 - src2) & ((1<<(self.rwidth))-1)
 237         self.regs[dest] = val
 238
 239     def setval(self, dest, val):
 240         self.regs[dest] = val
 241
 242     def dump(self, dut):
 243         for i, val in enumerate(self.regs):
 244             reg = yield dut.intregs.regs[i].reg
 245             okstr = "OK" if reg == val else "!ok"
 246             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
 247
 248     def check(self, dut):
 249         for i, val in enumerate(self.regs):
 250             reg = yield dut.intregs.regs[i].reg
 251             if reg != val:
 252                 print("reg %d expected %x received %x\n" % (i, val, reg))
 253                 yield from self.dump(dut)
 254                 assert False
 255
 256 def int_instr(dut, alusim, op, src1, src2, dest):
 257     for i in range(len(dut.int_insn_i)):
 258         yield dut.int_insn_i[i].eq(0)
 259     yield dut.int_dest_i.eq(dest)
 260     yield dut.int_src1_i.eq(src1)
 261     yield dut.int_src2_i.eq(src2)
 262     yield dut.int_insn_i[op].eq(1)
 263     alusim.op(op, src1, src2, dest)
 264
 265
 266 def print_reg(dut, rnums):
 267     rs = []
 268     for rnum in rnums:
 269         reg = yield dut.intregs.regs[rnum].reg
 270         rs.append("%x" % reg)
 271     rnums = map(str, rnums)
 272     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 273
 274
 275 def scoreboard_sim(dut, alusim):
 276     yield dut.int_store_i.eq(0)
 277
 278     for i in range(1, dut.n_regs):
 279         yield dut.intregs.regs[i].reg.eq(i)
 280         alusim.setval(i, i)
 281
 282     if False:
 283         yield from int_instr(dut, alusim, IADD, 4, 3, 5)
 284         yield from print_reg(dut, [3,4,5])
 285         yield
 286         yield from int_instr(dut, alusim, IADD, 5, 2, 5)
 287         yield from print_reg(dut, [3,4,5])
 288         yield
 289         yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
 290         yield from print_reg(dut, [3,4,5])
 291         yield
 292         for i in range(len(dut.int_insn_i)):
 293             yield dut.int_insn_i[i].eq(0)
 294         yield from print_reg(dut, [3,4,5])
 295         yield
 296         yield from print_reg(dut, [3,4,5])
 297         yield
 298         yield from print_reg(dut, [3,4,5])
 299         yield
 300
 301         yield from alusim.check(dut)
 302
 303     for i in range(100):
 304         src1 = randint(1, dut.n_regs-1)
 305         src2 = randint(1, dut.n_regs-1)
 306         while True:
 307             dest = randint(1, dut.n_regs-1)
 308             break
 309             if dest not in [src1, src2]:
 310                 break
 311         #src1 = 7
 312         #src2 = 7
 313         dest = src2
 314
 315         op = randint(0, 1)
 316         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
 317         yield from int_instr(dut, alusim, op, src1, src2, dest)
 318         yield from print_reg(dut, [3,4,5])
 319         yield
 320         yield from print_reg(dut, [3,4,5])
 321         for i in range(len(dut.int_insn_i)):
 322             yield dut.int_insn_i[i].eq(0)
 323         yield
 324         yield
 325
 326
 327     yield
 328     yield from print_reg(dut, [3,4,5])
 329     yield
 330     yield from print_reg(dut, [3,4,5])
 331     yield
 332     yield
 333     yield
 334     yield
 335     yield from alusim.check(dut)
 336
 337
 338 def explore_groups(dut):
 339     from nmigen.hdl.ir import Fragment
 340     from nmigen.hdl.xfrm import LHSGroupAnalyzer
 341
 342     fragment = dut.elaborate(platform=None)
 343     fr = Fragment.get(fragment, platform=None)
 344
 345     groups = LHSGroupAnalyzer()(fragment._statements)
 346
 347     print (groups)
 348
 349
 350 def test_scoreboard():
 351     dut = Scoreboard(32, 8)
 352     alusim = RegSim(32, 8)
 353     vl = rtlil.convert(dut, ports=dut.ports())
 354     with open("test_scoreboard6600.il", "w") as f:
 355         f.write(vl)
 356
 357     run_simulation(dut, scoreboard_sim(dut, alusim),
 358                         vcd_name='test_scoreboard6600.vcd')
 359
 360
 361 if __name__ == '__main__':
 362     test_scoreboard()