src/experiment/score6600.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18 from random import randint
  19
  20
  21 class Scoreboard(Elaboratable):
  22     def __init__(self, rwid, n_regs):
  23         """ Inputs:
  24
  25             * :rwid:   bit width of register file(s) - both FP and INT
  26             * :n_regs: depth of register file(s) - number of FP and INT regs
  27         """
  28         self.rwid = rwid
  29         self.n_regs = n_regs
  30
  31         # Register Files
  32         self.intregs = RegFileArray(rwid, n_regs)
  33         self.fpregs = RegFileArray(rwid, n_regs)
  34
  35         # inputs
  36         self.int_store_i = Signal(reset_less=True) # instruction is a store
  37         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  38         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  39         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  40
  41         self.issue_o = Signal(reset_less=True) # instruction was accepted
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45
  46         m.submodules.intregs = self.intregs
  47         m.submodules.fpregs = self.fpregs
  48
  49         # register ports
  50         int_dest = self.intregs.write_port("dest")
  51         int_src1 = self.intregs.read_port("src1")
  52         int_src2 = self.intregs.read_port("src2")
  53
  54         fp_dest = self.fpregs.write_port("dest")
  55         fp_src1 = self.fpregs.read_port("src1")
  56         fp_src2 = self.fpregs.read_port("src2")
  57
  58         # Int ALUs
  59         add = ALU(self.rwid)
  60         sub = ALU(self.rwid)
  61         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  62         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  63         int_alus = [comp1, comp2]
  64
  65         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  66         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  67
  68         # Count of number of FUs
  69         n_int_fus = len(int_alus)
  70         n_fp_fus = 0 # for now
  71
  72         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  73
  74         # Integer FU-FU Dep Matrix
  75         intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  76         m.submodules.intfudeps = intfudeps
  77         # Integer FU-Reg Dep Matrix
  78         intregdeps = FURegDepMatrix(self.n_regs, n_int_fus)
  79         m.submodules.intregdeps = intregdeps
  80
  81         # Integer Priority Picker 1: Adder + Subtractor
  82         intpick1 = GroupPicker(2) # picks between add and sub
  83         m.submodules.intpick1 = intpick1
  84
  85         # Global Pending Vectors (INT and TODO FP)
  86         g_int_src1_pend_v = intregdeps.rd_src2_pend_o
  87         g_int_src2_pend_v = intregdeps.rd_src1_pend_o
  88         g_int_rd_pend_v = intregdeps.rd_pend_o
  89         g_int_wr_pend_v = intregdeps.wr_pend_o
  90
  91         # INT/FP Issue Unit
  92         regdecode = RegDecode(self.n_regs)
  93         m.submodules.regdecode = regdecode
  94         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
  95         m.submodules.issueunit = issueunit
  96
  97         #---------
  98         # ok start wiring things together...
  99         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 100         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 101         #---------
 102
 103         #---------
 104         # Issue Unit is where it starts.  set up some in/outs for this module
 105         #---------
 106         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 107                      regdecode.dest_i.eq(self.int_dest_i),
 108                      regdecode.src1_i.eq(self.int_src1_i),
 109                      regdecode.src2_i.eq(self.int_src2_i),
 110                      regdecode.enable_i.eq(1),
 111                      issueunit.i.dest_i.eq(regdecode.dest_o),
 112                      self.issue_o.eq(issueunit.issue_o)
 113                     ]
 114         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 115
 116         # connect global rd/wr pending vectors
 117         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v)
 118         # TODO: issueunit.f (FP)
 119
 120         # and int function issue / busy arrays, and dest/src1/src2
 121         fn_issue_l = []
 122         fn_busy_l = []
 123         for i, alu in enumerate(int_alus):
 124             fn_issue_l.append(alu.issue_i)
 125             fn_busy_l.append(alu.busy_o)
 126
 127             #m.d.sync += alu.issue_i.eq(issueunit.i.fn_issue_o[i])
 128             #m.d.comb += alu.dest_i.eq(issueunit.i.dest_i)
 129             #m.d.comb += alu.src1_i.eq(issueunit.i.src1_i)
 130             #m.d.comb += alu.src2_i.eq(issueunit.i.src2_i)
 131             # XXX sync, so as to stop a simulation infinite loop
 132             #m.d.comb += issueunit.i.busy_i[i].eq(alu.busy_o)
 133             # NOTE: req_rel_o connected to picker, below.
 134
 135         #---------
 136         # connect Function Units
 137         #---------
 138
 139         # XXX sync, again to avoid an infinite loop.  is it the right thing???
 140
 141         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 142         #m.d.sync += if_l[0].go_rd_i.eq(intpick1.go_rd_o[0]) # add rd
 143         #m.d.sync += if_l[0].go_wr_i.eq(intpick1.go_wr_o[0]) # add wr
 144
 145         #m.d.sync += if_l[1].go_rd_i.eq(intpick1.go_rd_o[1]) # subtract rd
 146         #m.d.sync += if_l[1].go_wr_i.eq(intpick1.go_wr_o[1]) # subtract wr
 147
 148         # Connect Picker
 149         #---------
 150         m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
 151         m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
 152         int_readable_o = intfudeps.readable_o
 153         int_writable_o = intfudeps.writable_o
 154         m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
 155         m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
 156         m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
 157         m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
 158
 159         #---------
 160         # Connect Register File(s)
 161         #---------
 162         m.d.sync += int_dest.wen.eq(intregdeps.dest_rsel_o)
 163         m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
 164         m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
 165
 166         # merge (OR) all integer FU / ALU outputs to a single value
 167         # bit of a hack: treereduce needs a list with an item named "dest_o"
 168         dest_o = treereduce(int_alus)
 169         m.d.comb += int_dest.data_i.eq(dest_o)
 170
 171         # connect ALUs
 172         for i, alu in enumerate(int_alus):
 173             m.d.comb += alu.go_rd_i.eq(intpick1.go_rd_o[i])
 174             m.d.comb += alu.go_wr_i.eq(intpick1.go_wr_o[i])
 175             m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 176             #m.d.comb += fn_busy_l[i].eq(alu.busy_o)  # XXX ignore, use fnissue
 177             m.d.comb += alu.src1_i.eq(int_src1.data_o)
 178             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 179
 180         return m
 181
 182
 183     def __iter__(self):
 184         yield from self.intregs
 185         yield from self.fpregs
 186         yield self.int_store_i
 187         yield self.int_dest_i
 188         yield self.int_src1_i
 189         yield self.int_src2_i
 190         yield self.issue_o
 191         #yield from self.int_src1
 192         #yield from self.int_dest
 193         #yield from self.int_src1
 194         #yield from self.int_src2
 195         #yield from self.fp_dest
 196         #yield from self.fp_src1
 197         #yield from self.fp_src2
 198
 199     def ports(self):
 200         return list(self)
 201
 202 IADD = 0
 203 ISUB = 1
 204
 205 class RegSim:
 206     def __init__(self, rwidth, nregs):
 207         self.rwidth = rwidth
 208         self.regs = [0] * nregs
 209
 210     def op(self, op, src1, src2, dest):
 211         src1 = self.regs[src1]
 212         src2 = self.regs[src2]
 213         if op == IADD:
 214             val = (src1 + src2) & ((1<<(self.rwidth))-1)
 215         elif op == ISUB:
 216             val = (src1 - src2) & ((1<<(self.rwidth))-1)
 217         self.regs[dest] = val
 218
 219     def setval(self, dest, val):
 220         self.regs[dest] = val
 221
 222     def dump(self, dut):
 223         for i, val in enumerate(self.regs):
 224             reg = yield dut.intregs.regs[i].reg
 225             okstr = "OK" if reg == val else "!ok"
 226             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
 227
 228     def check(self, dut):
 229         for i, val in enumerate(self.regs):
 230             reg = yield dut.intregs.regs[i].reg
 231             if reg != val:
 232                 print("reg %d expected %x received %x\n" % (i, val, reg))
 233                 yield from self.dump(dut)
 234                 assert False
 235
 236 def int_instr(dut, alusim, op, src1, src2, dest):
 237     for i in range(len(dut.int_insn_i)):
 238         yield dut.int_insn_i[i].eq(0)
 239     yield dut.int_dest_i.eq(dest)
 240     yield dut.int_src1_i.eq(src1)
 241     yield dut.int_src2_i.eq(src2)
 242     yield dut.int_insn_i[op].eq(1)
 243     alusim.op(op, src1, src2, dest)
 244
 245
 246 def print_reg(dut, rnums):
 247     rs = []
 248     for rnum in rnums:
 249         reg = yield dut.intregs.regs[rnum].reg
 250         rs.append("%x" % reg)
 251     rnums = map(str, rnums)
 252     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 253
 254
 255 def scoreboard_sim(dut, alusim):
 256     yield dut.int_store_i.eq(0)
 257
 258     for i in range(1, dut.n_regs):
 259         yield dut.intregs.regs[i].reg.eq(i)
 260         alusim.setval(i, i)
 261
 262     if False:
 263         yield from int_instr(dut, alusim, IADD, 4, 3, 5)
 264         yield from print_reg(dut, [3,4,5])
 265         yield
 266         yield from int_instr(dut, alusim, IADD, 5, 2, 5)
 267         yield from print_reg(dut, [3,4,5])
 268         yield
 269         yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
 270         yield from print_reg(dut, [3,4,5])
 271         yield
 272         for i in range(len(dut.int_insn_i)):
 273             yield dut.int_insn_i[i].eq(0)
 274         yield from print_reg(dut, [3,4,5])
 275         yield
 276         yield from print_reg(dut, [3,4,5])
 277         yield
 278         yield from print_reg(dut, [3,4,5])
 279         yield
 280
 281         yield from alusim.check(dut)
 282
 283     for i in range(100):
 284         src1 = randint(1, dut.n_regs-1)
 285         src2 = randint(1, dut.n_regs-1)
 286         while True:
 287             dest = randint(1, dut.n_regs-1)
 288             break
 289             if dest not in [src1, src2]:
 290                 break
 291         #src1 = 7
 292         #src2 = 7
 293         dest = src2
 294
 295         op = randint(0, 1)
 296         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
 297         yield from int_instr(dut, alusim, op, src1, src2, dest)
 298         yield from print_reg(dut, [3,4,5])
 299         yield
 300         yield from print_reg(dut, [3,4,5])
 301         for i in range(len(dut.int_insn_i)):
 302             yield dut.int_insn_i[i].eq(0)
 303         yield
 304         yield
 305
 306
 307     yield
 308     yield from print_reg(dut, [3,4,5])
 309     yield
 310     yield from print_reg(dut, [3,4,5])
 311     yield
 312     yield
 313     yield
 314     yield
 315     yield from alusim.check(dut)
 316
 317
 318 def explore_groups(dut):
 319     from nmigen.hdl.ir import Fragment
 320     from nmigen.hdl.xfrm import LHSGroupAnalyzer
 321
 322     fragment = dut.elaborate(platform=None)
 323     fr = Fragment.get(fragment, platform=None)
 324
 325     groups = LHSGroupAnalyzer()(fragment._statements)
 326
 327     print (groups)
 328
 329
 330 def test_scoreboard():
 331     dut = Scoreboard(32, 8)
 332     alusim = RegSim(32, 8)
 333     vl = rtlil.convert(dut, ports=dut.ports())
 334     with open("test_scoreboard6600.il", "w") as f:
 335         f.write(vl)
 336
 337     run_simulation(dut, scoreboard_sim(dut, alusim),
 338                         vcd_name='test_scoreboard6600.vcd')
 339
 340
 341 if __name__ == '__main__':
 342     test_scoreboard()