1 from nmigen
.compat
.sim
import run_simulation
2 from nmigen
.cli
import verilog
, rtlil
3 from nmigen
import Module
, Const
, Signal
, Array
, Cat
, Elaboratable
5 from regfile
.regfile
import RegFileArray
, treereduce
6 from scoreboard
.fn_unit
import IntFnUnit
, FPFnUnit
, LDFnUnit
, STFnUnit
7 from scoreboard
.fu_fu_matrix
import FUFUDepMatrix
8 from scoreboard
.fu_reg_matrix
import FURegDepMatrix
9 from scoreboard
.global_pending
import GlobalPending
10 from scoreboard
.group_picker
import GroupPicker
11 from scoreboard
.issue_unit
import IntFPIssueUnit
, RegDecode
13 from compalu
import ComputationUnitNoDelay
15 from alu_hier
import ALU
16 from nmutil
.latch
import SRLatch
18 from random
import randint
21 class Scoreboard(Elaboratable
):
22 def __init__(self
, rwid
, n_regs
):
25 * :rwid: bit width of register file(s) - both FP and INT
26 * :n_regs: depth of register file(s) - number of FP and INT regs
32 self
.intregs
= RegFileArray(rwid
, n_regs
)
33 self
.fpregs
= RegFileArray(rwid
, n_regs
)
36 self
.int_store_i
= Signal(reset_less
=True) # instruction is a store
37 self
.int_dest_i
= Signal(max=n_regs
, reset_less
=True) # Dest R# in
38 self
.int_src1_i
= Signal(max=n_regs
, reset_less
=True) # oper1 R# in
39 self
.int_src2_i
= Signal(max=n_regs
, reset_less
=True) # oper2 R# in
41 self
.issue_o
= Signal(reset_less
=True) # instruction was accepted
43 def elaborate(self
, platform
):
46 m
.submodules
.intregs
= self
.intregs
47 m
.submodules
.fpregs
= self
.fpregs
50 int_dest
= self
.intregs
.write_port("dest")
51 int_src1
= self
.intregs
.read_port("src1")
52 int_src2
= self
.intregs
.read_port("src2")
54 fp_dest
= self
.fpregs
.write_port("dest")
55 fp_src1
= self
.fpregs
.read_port("src1")
56 fp_src2
= self
.fpregs
.read_port("src2")
61 m
.submodules
.comp1
= comp1
= ComputationUnitNoDelay(self
.rwid
, 1, add
)
62 m
.submodules
.comp2
= comp2
= ComputationUnitNoDelay(self
.rwid
, 1, sub
)
63 int_alus
= [comp1
, comp2
]
65 m
.d
.comb
+= comp1
.oper_i
.eq(Const(0)) # temporary/experiment: op=add
66 m
.d
.comb
+= comp2
.oper_i
.eq(Const(1)) # temporary/experiment: op=sub
74 for i
, a
in enumerate(int_alus
):
75 # set up Integer Function Unit, add to module (and python list)
76 fu
= IntFnUnit(self
.n_regs
, shadow_wid
=0)
77 setattr(m
.submodules
, "intfu%d" % i
, fu
)
79 # collate the read/write pending vectors (to go into global pending)
80 int_src1_pend_v
.append(fu
.src1_pend_o
)
81 int_src2_pend_v
.append(fu
.src2_pend_o
)
82 int_rd_pend_v
.append(fu
.int_rd_pend_o
)
83 int_wr_pend_v
.append(fu
.int_wr_pend_o
)
86 # Count of number of FUs
88 n_fp_fus
= 0 # for now
90 n_fus
= n_int_fus
+ n_fp_fus
# plus FP FUs
92 # Integer FU-FU Dep Matrix
93 intfudeps
= FUFUDepMatrix(n_int_fus
, n_int_fus
)
94 m
.submodules
.intfudeps
= intfudeps
95 # Integer FU-Reg Dep Matrix
96 intregdeps
= FURegDepMatrix(n_int_fus
, self
.n_regs
)
97 m
.submodules
.intregdeps
= intregdeps
99 # Integer Priority Picker 1: Adder + Subtractor
100 intpick1
= GroupPicker(2) # picks between add and sub
101 m
.submodules
.intpick1
= intpick1
103 # Global Pending Vectors (INT and TODO FP)
104 # NOTE: number of vectors is NOT same as number of FUs.
105 g_int_src1_pend_v
= GlobalPending(self
.n_regs
, int_src1_pend_v
)
106 g_int_src2_pend_v
= GlobalPending(self
.n_regs
, int_src2_pend_v
)
107 g_int_rd_pend_v
= GlobalPending(self
.n_regs
, int_rd_pend_v
)
108 g_int_wr_pend_v
= GlobalPending(self
.n_regs
, int_wr_pend_v
)
109 m
.submodules
.g_int_src1_pend_v
= g_int_src1_pend_v
110 m
.submodules
.g_int_src2_pend_v
= g_int_src2_pend_v
111 m
.submodules
.g_int_rd_pend_v
= g_int_rd_pend_v
112 m
.submodules
.g_int_wr_pend_v
= g_int_wr_pend_v
115 regdecode
= RegDecode(self
.n_regs
)
116 m
.submodules
.regdecode
= regdecode
117 issueunit
= IntFPIssueUnit(self
.n_regs
, n_int_fus
, n_fp_fus
)
118 m
.submodules
.issueunit
= issueunit
121 # ok start wiring things together...
122 # "now hear de word of de looord... dem bones dem bones dem dryy bones"
123 # https://www.youtube.com/watch?v=pYb8Wm6-QfA
127 # Issue Unit is where it starts. set up some in/outs for this module
129 m
.d
.comb
+= [issueunit
.i
.store_i
.eq(self
.int_store_i
),
130 regdecode
.dest_i
.eq(self
.int_dest_i
),
131 regdecode
.src1_i
.eq(self
.int_src1_i
),
132 regdecode
.src2_i
.eq(self
.int_src2_i
),
133 regdecode
.enable_i
.eq(1),
134 issueunit
.i
.dest_i
.eq(regdecode
.dest_o
),
135 self
.issue_o
.eq(issueunit
.issue_o
)
137 self
.int_insn_i
= issueunit
.i
.insn_i
# enabled by instruction decode
139 # connect global rd/wr pending vectors
140 m
.d
.comb
+= issueunit
.i
.g_wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
141 # TODO: issueunit.f (FP)
143 # and int function issue / busy arrays, and dest/src1/src2
146 for i
, fu
in enumerate(if_l
):
147 fn_issue_l
.append(fu
.issue_i
)
148 fn_busy_l
.append(fu
.busy_o
)
149 m
.d
.sync
+= fu
.issue_i
.eq(issueunit
.i
.fn_issue_o
[i
])
150 m
.d
.sync
+= fu
.dest_i
.eq(self
.int_dest_i
)
151 m
.d
.sync
+= fu
.src1_i
.eq(self
.int_src1_i
)
152 m
.d
.sync
+= fu
.src2_i
.eq(self
.int_src2_i
)
153 # XXX sync, so as to stop a simulation infinite loop
154 m
.d
.sync
+= issueunit
.i
.busy_i
[i
].eq(fu
.busy_o
)
156 fn_issue_o
= Signal(len(fn_issue_l
), reset_less
=True)
157 m
.d
.comb
+= fn_issue_o
.eq(Cat(*fn_issue_l
))
158 #fn_issue_o = issueunit.i.fn_issue_o
160 # connect fu-fu matrix
163 m
.d
.comb
+= intfudeps
.rd_pend_i
.eq(g_int_rd_pend_v
.g_pend_o
)
164 m
.d
.comb
+= intfudeps
.wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
166 # Group Picker... done manually for now. TODO: cat array of pick sigs
167 go_rd_o
= intpick1
.go_rd_o
168 go_wr_o
= intpick1
.go_wr_o
169 go_rd_i
= intfudeps
.go_rd_i
170 go_wr_i
= intfudeps
.go_wr_i
171 m
.d
.comb
+= go_rd_i
[0].eq(go_rd_o
[0]) # add rd
172 m
.d
.comb
+= go_wr_i
[0].eq(go_wr_o
[0]) # add wr
174 m
.d
.comb
+= go_rd_i
[1].eq(go_rd_o
[1]) # sub rd
175 m
.d
.comb
+= go_wr_i
[1].eq(go_wr_o
[1]) # sub wr
177 m
.d
.comb
+= intfudeps
.issue_i
.eq(fn_issue_o
)
179 # Connect INT FU go_rd/wr
180 for i
, fu
in enumerate(if_l
):
181 m
.d
.comb
+= fu
.go_rd_i
.eq(go_rd_o
[i
])
182 m
.d
.comb
+= fu
.go_wr_i
.eq(go_wr_o
[i
])
184 # Connect INT Fn Unit global wr/rd pending
186 m
.d
.comb
+= fu
.g_int_wr_pend_i
.eq(g_int_wr_pend_v
.g_pend_o
)
187 m
.d
.comb
+= fu
.g_int_rd_pend_i
.eq(g_int_rd_pend_v
.g_pend_o
)
190 # connect fu-dep matrix
192 r_go_rd_i
= intregdeps
.go_rd_i
193 r_go_wr_i
= intregdeps
.go_wr_i
194 m
.d
.comb
+= r_go_rd_i
.eq(go_rd_o
)
195 m
.d
.comb
+= r_go_wr_i
.eq(go_wr_o
)
197 m
.d
.comb
+= intregdeps
.dest_i
.eq(regdecode
.dest_o
)
198 m
.d
.comb
+= intregdeps
.src1_i
.eq(regdecode
.src1_o
)
199 m
.d
.comb
+= intregdeps
.src2_i
.eq(regdecode
.src2_o
)
200 m
.d
.comb
+= intregdeps
.issue_i
.eq(fn_issue_o
)
204 m
.d
.sync
+= intpick1
.req_rel_i
[0].eq(int_alus
[0].req_rel_o
)
205 m
.d
.sync
+= intpick1
.req_rel_i
[1].eq(int_alus
[1].req_rel_o
)
206 int_readable_o
= intfudeps
.readable_o
207 int_writable_o
= intfudeps
.writable_o
208 m
.d
.comb
+= intpick1
.readable_i
[0].eq(int_readable_o
[0]) # add rd
209 m
.d
.comb
+= intpick1
.writable_i
[0].eq(int_writable_o
[0]) # add wr
210 m
.d
.comb
+= intpick1
.readable_i
[1].eq(int_readable_o
[1]) # sub rd
211 m
.d
.comb
+= intpick1
.writable_i
[1].eq(int_writable_o
[1]) # sub wr
214 # Connect Register File(s)
216 print ("intregdeps wen len", len(intregdeps
.dest_rsel_o
))
217 m
.d
.comb
+= int_dest
.wen
.eq(intregdeps
.dest_rsel_o
)
218 m
.d
.comb
+= int_src1
.ren
.eq(intregdeps
.src1_rsel_o
)
219 m
.d
.comb
+= int_src2
.ren
.eq(intregdeps
.src2_rsel_o
)
221 # merge (OR) all integer FU / ALU outputs to a single value
222 # bit of a hack: treereduce needs a list with an item named "dest_o"
223 dest_o
= treereduce(int_alus
)
224 m
.d
.comb
+= int_dest
.data_i
.eq(dest_o
)
227 for i
, alu
in enumerate(int_alus
):
228 m
.d
.comb
+= alu
.go_rd_i
.eq(go_rd_o
[i
])
229 m
.d
.comb
+= alu
.go_wr_i
.eq(go_wr_o
[i
])
230 m
.d
.comb
+= alu
.issue_i
.eq(fn_issue_l
[i
])
231 m
.d
.comb
+= alu
.src1_i
.eq(int_src1
.data_o
)
232 m
.d
.comb
+= alu
.src2_i
.eq(int_src2
.data_o
)
233 m
.d
.sync
+= if_l
[i
].req_rel_i
.eq(alu
.req_rel_o
) # pipe out ready
239 yield from self
.intregs
240 yield from self
.fpregs
241 yield self
.int_store_i
242 yield self
.int_dest_i
243 yield self
.int_src1_i
244 yield self
.int_src2_i
246 #yield from self.int_src1
247 #yield from self.int_dest
248 #yield from self.int_src1
249 #yield from self.int_src2
250 #yield from self.fp_dest
251 #yield from self.fp_src1
252 #yield from self.fp_src2
261 def __init__(self
, rwidth
, nregs
):
263 self
.regs
= [0] * nregs
265 def op(self
, op
, src1
, src2
, dest
):
266 src1
= self
.regs
[src1
]
267 src2
= self
.regs
[src2
]
269 val
= (src1
+ src2
) & ((1<<(self
.rwidth
))-1)
271 val
= (src1
- src2
) & ((1<<(self
.rwidth
))-1)
272 self
.regs
[dest
] = val
274 def setval(self
, dest
, val
):
275 self
.regs
[dest
] = val
278 for i
, val
in enumerate(self
.regs
):
279 reg
= yield dut
.intregs
.regs
[i
].reg
280 okstr
= "OK" if reg
== val
else "!ok"
281 print("reg %d expected %x received %x %s" % (i
, val
, reg
, okstr
))
283 def check(self
, dut
):
284 for i
, val
in enumerate(self
.regs
):
285 reg
= yield dut
.intregs
.regs
[i
].reg
287 print("reg %d expected %x received %x\n" % (i
, val
, reg
))
288 yield from self
.dump(dut
)
291 def int_instr(dut
, alusim
, op
, src1
, src2
, dest
):
292 for i
in range(len(dut
.int_insn_i
)):
293 yield dut
.int_insn_i
[i
].eq(0)
294 yield dut
.int_dest_i
.eq(dest
)
295 yield dut
.int_src1_i
.eq(src1
)
296 yield dut
.int_src2_i
.eq(src2
)
297 yield dut
.int_insn_i
[op
].eq(1)
298 alusim
.op(op
, src1
, src2
, dest
)
301 def print_reg(dut
, rnums
):
304 reg
= yield dut
.intregs
.regs
[rnum
].reg
305 rs
.append("%x" % reg
)
306 rnums
= map(str, rnums
)
307 print ("reg %s: %s" % (','.join(rnums
), ','.join(rs
)))
310 def scoreboard_sim(dut
, alusim
):
311 yield dut
.int_store_i
.eq(0)
313 for i
in range(1, dut
.n_regs
):
314 yield dut
.intregs
.regs
[i
].reg
.eq(i
)
321 yield from int_instr(dut
, alusim
, IADD
, 4, 3, 5)
322 yield from print_reg(dut
, [3,4,5])
324 yield from int_instr(dut
, alusim
, IADD
, 5, 2, 5)
325 yield from print_reg(dut
, [3,4,5])
327 yield from int_instr(dut
, alusim
, ISUB
, 5, 1, 3)
328 yield from print_reg(dut
, [3,4,5])
330 for i
in range(len(dut
.int_insn_i
)):
331 yield dut
.int_insn_i
[i
].eq(0)
332 yield from print_reg(dut
, [3,4,5])
334 yield from print_reg(dut
, [3,4,5])
336 yield from print_reg(dut
, [3,4,5])
339 yield from alusim
.check(dut
)
342 src1
= randint(1, dut
.n_regs
-1)
343 src2
= randint(1, dut
.n_regs
-1)
345 dest
= randint(1, dut
.n_regs
-1)
347 if dest
not in [src1
, src2
]:
355 print ("random %d: %d %d %d %d\n" % (i
, op
, src1
, src2
, dest
))
356 yield from int_instr(dut
, alusim
, op
, src1
, src2
, dest
)
357 yield from print_reg(dut
, [3,4,5])
359 yield from print_reg(dut
, [3,4,5])
360 for i
in range(len(dut
.int_insn_i
)):
361 yield dut
.int_insn_i
[i
].eq(0)
368 yield from print_reg(dut
, [3,4,5])
370 yield from print_reg(dut
, [3,4,5])
375 yield from alusim
.check(dut
)
376 yield from alusim
.dump(dut
)
379 def explore_groups(dut
):
380 from nmigen
.hdl
.ir
import Fragment
381 from nmigen
.hdl
.xfrm
import LHSGroupAnalyzer
383 fragment
= dut
.elaborate(platform
=None)
384 fr
= Fragment
.get(fragment
, platform
=None)
386 groups
= LHSGroupAnalyzer()(fragment
._statements
)
391 def test_scoreboard():
392 dut
= Scoreboard(32, 8)
393 alusim
= RegSim(32, 8)
394 vl
= rtlil
.convert(dut
, ports
=dut
.ports())
395 with
open("test_scoreboard6600.il", "w") as f
:
398 run_simulation(dut
, scoreboard_sim(dut
, alusim
),
399 vcd_name
='test_scoreboard6600.vcd')
402 if __name__
== '__main__':