src/experiment/score6600.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Const, Signal, Array, Cat, Elaboratable
   4
   5 from regfile.regfile import RegFileArray, treereduce
   6 from scoreboard.fn_unit import IntFnUnit, FPFnUnit, LDFnUnit, STFnUnit
   7 from scoreboard.fu_fu_matrix import FUFUDepMatrix
   8 from scoreboard.fu_reg_matrix import FURegDepMatrix
   9 from scoreboard.global_pending import GlobalPending
  10 from scoreboard.group_picker import GroupPicker
  11 from scoreboard.issue_unit import IntFPIssueUnit, RegDecode
  12
  13 from compalu import ComputationUnitNoDelay
  14
  15 from alu_hier import ALU
  16 from nmutil.latch import SRLatch
  17
  18 from random import randint
  19
  20
  21 class Scoreboard(Elaboratable):
  22     def __init__(self, rwid, n_regs):
  23         """ Inputs:
  24
  25             * :rwid:   bit width of register file(s) - both FP and INT
  26             * :n_regs: depth of register file(s) - number of FP and INT regs
  27         """
  28         self.rwid = rwid
  29         self.n_regs = n_regs
  30
  31         # Register Files
  32         self.intregs = RegFileArray(rwid, n_regs)
  33         self.fpregs = RegFileArray(rwid, n_regs)
  34
  35         # inputs
  36         self.int_store_i = Signal(reset_less=True) # instruction is a store
  37         self.int_dest_i = Signal(max=n_regs, reset_less=True) # Dest R# in
  38         self.int_src1_i = Signal(max=n_regs, reset_less=True) # oper1 R# in
  39         self.int_src2_i = Signal(max=n_regs, reset_less=True) # oper2 R# in
  40
  41         self.issue_o = Signal(reset_less=True) # instruction was accepted
  42
  43     def elaborate(self, platform):
  44         m = Module()
  45
  46         m.submodules.intregs = self.intregs
  47         m.submodules.fpregs = self.fpregs
  48
  49         # register ports
  50         int_dest = self.intregs.write_port("dest")
  51         int_src1 = self.intregs.read_port("src1")
  52         int_src2 = self.intregs.read_port("src2")
  53
  54         fp_dest = self.fpregs.write_port("dest")
  55         fp_src1 = self.fpregs.read_port("src1")
  56         fp_src2 = self.fpregs.read_port("src2")
  57
  58         # Int ALUs
  59         add = ALU(self.rwid)
  60         sub = ALU(self.rwid)
  61         m.submodules.comp1 = comp1 = ComputationUnitNoDelay(self.rwid, 1, add)
  62         m.submodules.comp2 = comp2 = ComputationUnitNoDelay(self.rwid, 1, sub)
  63         int_alus = [comp1, comp2]
  64
  65         m.d.comb += comp1.oper_i.eq(Const(0)) # temporary/experiment: op=add
  66         m.d.comb += comp2.oper_i.eq(Const(1)) # temporary/experiment: op=sub
  67
  68         # Int FUs
  69         if_l = []
  70         int_src1_pend_v = []
  71         int_src2_pend_v = []
  72         int_rd_pend_v = []
  73         int_wr_pend_v = []
  74         for i, a in enumerate(int_alus):
  75             # set up Integer Function Unit, add to module (and python list)
  76             fu = IntFnUnit(self.n_regs, shadow_wid=0)
  77             setattr(m.submodules, "intfu%d" % i, fu)
  78             if_l.append(fu)
  79             # collate the read/write pending vectors (to go into global pending)
  80             int_src1_pend_v.append(fu.src1_pend_o)
  81             int_src2_pend_v.append(fu.src2_pend_o)
  82             int_rd_pend_v.append(fu.int_rd_pend_o)
  83             int_wr_pend_v.append(fu.int_wr_pend_o)
  84         int_fus = Array(if_l)
  85
  86         # Count of number of FUs
  87         n_int_fus = len(if_l)
  88         n_fp_fus = 0 # for now
  89
  90         n_fus = n_int_fus + n_fp_fus # plus FP FUs
  91
  92         # Integer FU-FU Dep Matrix
  93         intfudeps = FUFUDepMatrix(n_int_fus, n_int_fus)
  94         m.submodules.intfudeps = intfudeps
  95         # Integer FU-Reg Dep Matrix
  96         intregdeps = FURegDepMatrix(n_int_fus, self.n_regs)
  97         m.submodules.intregdeps = intregdeps
  98
  99         # Integer Priority Picker 1: Adder + Subtractor
 100         intpick1 = GroupPicker(2) # picks between add and sub
 101         m.submodules.intpick1 = intpick1
 102
 103         # Global Pending Vectors (INT and TODO FP)
 104         # NOTE: number of vectors is NOT same as number of FUs.
 105         g_int_src1_pend_v = GlobalPending(self.n_regs, int_src1_pend_v)
 106         g_int_src2_pend_v = GlobalPending(self.n_regs, int_src2_pend_v)
 107         g_int_rd_pend_v = GlobalPending(self.n_regs, int_rd_pend_v)
 108         g_int_wr_pend_v = GlobalPending(self.n_regs, int_wr_pend_v)
 109         m.submodules.g_int_src1_pend_v = g_int_src1_pend_v
 110         m.submodules.g_int_src2_pend_v = g_int_src2_pend_v
 111         m.submodules.g_int_rd_pend_v = g_int_rd_pend_v
 112         m.submodules.g_int_wr_pend_v = g_int_wr_pend_v
 113
 114         # INT/FP Issue Unit
 115         regdecode = RegDecode(self.n_regs)
 116         m.submodules.regdecode = regdecode
 117         issueunit = IntFPIssueUnit(self.n_regs, n_int_fus, n_fp_fus)
 118         m.submodules.issueunit = issueunit
 119
 120         #---------
 121         # ok start wiring things together...
 122         # "now hear de word of de looord... dem bones dem bones dem dryy bones"
 123         # https://www.youtube.com/watch?v=pYb8Wm6-QfA
 124         #---------
 125
 126         #---------
 127         # Issue Unit is where it starts.  set up some in/outs for this module
 128         #---------
 129         m.d.comb += [issueunit.i.store_i.eq(self.int_store_i),
 130                      regdecode.dest_i.eq(self.int_dest_i),
 131                      regdecode.src1_i.eq(self.int_src1_i),
 132                      regdecode.src2_i.eq(self.int_src2_i),
 133                      regdecode.enable_i.eq(1),
 134                      issueunit.i.dest_i.eq(regdecode.dest_o),
 135                      self.issue_o.eq(issueunit.issue_o)
 136                     ]
 137         self.int_insn_i = issueunit.i.insn_i # enabled by instruction decode
 138
 139         # connect global rd/wr pending vectors
 140         m.d.comb += issueunit.i.g_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 141         # TODO: issueunit.f (FP)
 142
 143         # and int function issue / busy arrays, and dest/src1/src2
 144         fn_busy_l = []
 145         fn_issue_l = []
 146         for i, fu in enumerate(if_l):
 147             fn_issue_l.append(fu.issue_i)
 148             fn_busy_l.append(fu.busy_o)
 149             m.d.sync += fu.issue_i.eq(issueunit.i.fn_issue_o[i])
 150             m.d.comb += fu.dest_i.eq(self.int_dest_i)
 151             m.d.comb += fu.src1_i.eq(self.int_src1_i)
 152             m.d.comb += fu.src2_i.eq(self.int_src2_i)
 153             # XXX sync, so as to stop a simulation infinite loop
 154             m.d.comb += issueunit.i.busy_i[i].eq(fu.busy_o)
 155
 156         fn_issue_o = Signal(len(fn_issue_l), reset_less=True)
 157         m.d.comb += fn_issue_o.eq(Cat(*fn_issue_l))
 158         #fn_issue_o = issueunit.i.fn_issue_o
 159         #---------
 160         # connect fu-fu matrix
 161         #---------
 162
 163         m.d.comb += intfudeps.rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 164         m.d.comb += intfudeps.wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 165
 166         # Group Picker... done manually for now.  TODO: cat array of pick sigs
 167         go_rd_i = intfudeps.go_rd_i
 168         go_wr_i = intfudeps.go_wr_i
 169         m.d.comb += go_rd_i[0].eq(intpick1.go_rd_o[0]) # add rd
 170         m.d.comb += go_wr_i[0].eq(intpick1.go_wr_o[0]) # add wr
 171
 172         m.d.comb += go_rd_i[1].eq(intpick1.go_rd_o[1]) # sub rd
 173         m.d.comb += go_wr_i[1].eq(intpick1.go_wr_o[1]) # sub wr
 174
 175         m.d.comb += intfudeps.issue_i.eq(fn_issue_o)
 176
 177         # Connect INT Fn Unit global wr/rd pending
 178         for fu in if_l:
 179             m.d.comb += fu.g_int_wr_pend_i.eq(g_int_wr_pend_v.g_pend_o)
 180             m.d.comb += fu.g_int_rd_pend_i.eq(g_int_rd_pend_v.g_pend_o)
 181
 182         #---------
 183         # connect fu-dep matrix
 184         #---------
 185         r_go_rd_i = intregdeps.go_rd_i
 186         r_go_wr_i = intregdeps.go_wr_i
 187         m.d.comb += r_go_rd_i.eq(go_rd_i)
 188         m.d.comb += r_go_wr_i.eq(go_wr_i)
 189
 190         m.d.comb += intregdeps.dest_i.eq(regdecode.dest_o)
 191         m.d.comb += intregdeps.src1_i.eq(regdecode.src1_o)
 192         m.d.comb += intregdeps.src2_i.eq(regdecode.src2_o)
 193         m.d.comb += intregdeps.issue_i.eq(fn_issue_o)
 194
 195         # Connect Picker
 196         #---------
 197         m.d.comb += intpick1.req_rel_i[0].eq(int_alus[0].req_rel_o)
 198         m.d.comb += intpick1.req_rel_i[1].eq(int_alus[1].req_rel_o)
 199         int_readable_o = intfudeps.readable_o
 200         int_writable_o = intfudeps.writable_o
 201         m.d.comb += intpick1.readable_i[0].eq(int_readable_o[0]) # add rd
 202         m.d.comb += intpick1.writable_i[0].eq(int_writable_o[0]) # add wr
 203         m.d.comb += intpick1.readable_i[1].eq(int_readable_o[1]) # sub rd
 204         m.d.comb += intpick1.writable_i[1].eq(int_writable_o[1]) # sub wr
 205
 206         #---------
 207         # Connect Register File(s)
 208         #---------
 209         m.d.comb += int_dest.wen.eq(intregdeps.dest_rsel_o)
 210         m.d.comb += int_src1.ren.eq(intregdeps.src1_rsel_o)
 211         m.d.comb += int_src2.ren.eq(intregdeps.src2_rsel_o)
 212
 213         # merge (OR) all integer FU / ALU outputs to a single value
 214         # bit of a hack: treereduce needs a list with an item named "dest_o"
 215         dest_o = treereduce(int_alus)
 216         m.d.comb += int_dest.data_i.eq(dest_o)
 217
 218         # connect ALUs
 219         for i, alu in enumerate(int_alus):
 220             m.d.comb += alu.go_rd_i.eq(if_l[i].go_rd_i)
 221             m.d.comb += alu.go_wr_i.eq(if_l[i].go_wr_i)
 222             m.d.comb += alu.issue_i.eq(fn_issue_l[i])
 223             m.d.comb += alu.src1_i.eq(int_src1.data_o)
 224             m.d.comb += alu.src2_i.eq(int_src2.data_o)
 225             m.d.comb += if_l[i].req_rel_i.eq(alu.req_rel_o) # pipe out ready
 226
 227         return m
 228
 229
 230     def __iter__(self):
 231         yield from self.intregs
 232         yield from self.fpregs
 233         yield self.int_store_i
 234         yield self.int_dest_i
 235         yield self.int_src1_i
 236         yield self.int_src2_i
 237         yield self.issue_o
 238         #yield from self.int_src1
 239         #yield from self.int_dest
 240         #yield from self.int_src1
 241         #yield from self.int_src2
 242         #yield from self.fp_dest
 243         #yield from self.fp_src1
 244         #yield from self.fp_src2
 245
 246     def ports(self):
 247         return list(self)
 248
 249 IADD = 0
 250 ISUB = 1
 251
 252 class RegSim:
 253     def __init__(self, rwidth, nregs):
 254         self.rwidth = rwidth
 255         self.regs = [0] * nregs
 256
 257     def op(self, op, src1, src2, dest):
 258         src1 = self.regs[src1]
 259         src2 = self.regs[src2]
 260         if op == IADD:
 261             val = (src1 + src2) & ((1<<(self.rwidth))-1)
 262         elif op == ISUB:
 263             val = (src1 - src2) & ((1<<(self.rwidth))-1)
 264         self.regs[dest] = val
 265
 266     def setval(self, dest, val):
 267         self.regs[dest] = val
 268
 269     def dump(self, dut):
 270         for i, val in enumerate(self.regs):
 271             reg = yield dut.intregs.regs[i].reg
 272             okstr = "OK" if reg == val else "!ok"
 273             print("reg %d expected %x received %x %s" % (i, val, reg, okstr))
 274
 275     def check(self, dut):
 276         for i, val in enumerate(self.regs):
 277             reg = yield dut.intregs.regs[i].reg
 278             if reg != val:
 279                 print("reg %d expected %x received %x\n" % (i, val, reg))
 280                 yield from self.dump(dut)
 281                 assert False
 282
 283 def int_instr(dut, alusim, op, src1, src2, dest):
 284     for i in range(len(dut.int_insn_i)):
 285         yield dut.int_insn_i[i].eq(0)
 286     yield dut.int_dest_i.eq(dest)
 287     yield dut.int_src1_i.eq(src1)
 288     yield dut.int_src2_i.eq(src2)
 289     yield dut.int_insn_i[op].eq(1)
 290     alusim.op(op, src1, src2, dest)
 291
 292
 293 def print_reg(dut, rnums):
 294     rs = []
 295     for rnum in rnums:
 296         reg = yield dut.intregs.regs[rnum].reg
 297         rs.append("%x" % reg)
 298     rnums = map(str, rnums)
 299     print ("reg %s: %s" % (','.join(rnums), ','.join(rs)))
 300
 301
 302 def scoreboard_sim(dut, alusim):
 303     yield dut.int_store_i.eq(0)
 304
 305     for i in range(1, dut.n_regs):
 306         yield dut.intregs.regs[i].reg.eq(i)
 307         alusim.setval(i, i)
 308
 309     if False:
 310         yield from int_instr(dut, alusim, IADD, 4, 3, 5)
 311         yield from print_reg(dut, [3,4,5])
 312         yield
 313         yield from int_instr(dut, alusim, IADD, 5, 2, 5)
 314         yield from print_reg(dut, [3,4,5])
 315         yield
 316         yield from int_instr(dut, alusim, ISUB, 5, 1, 3)
 317         yield from print_reg(dut, [3,4,5])
 318         yield
 319         for i in range(len(dut.int_insn_i)):
 320             yield dut.int_insn_i[i].eq(0)
 321         yield from print_reg(dut, [3,4,5])
 322         yield
 323         yield from print_reg(dut, [3,4,5])
 324         yield
 325         yield from print_reg(dut, [3,4,5])
 326         yield
 327
 328         yield from alusim.check(dut)
 329
 330     for i in range(4):
 331         src1 = randint(1, dut.n_regs-1)
 332         src2 = randint(1, dut.n_regs-1)
 333         while True:
 334             dest = randint(1, dut.n_regs-1)
 335             break
 336             if dest not in [src1, src2]:
 337                 break
 338         src1 = 1
 339         src2 = 7
 340         dest = src2
 341
 342         op = randint(0, 1)
 343         op = 0
 344         print ("random %d: %d %d %d %d\n" % (i, op, src1, src2, dest))
 345         yield from int_instr(dut, alusim, op, src1, src2, dest)
 346         yield from print_reg(dut, [3,4,5])
 347         yield
 348         yield from print_reg(dut, [3,4,5])
 349         for i in range(len(dut.int_insn_i)):
 350             yield dut.int_insn_i[i].eq(0)
 351         yield
 352         yield
 353
 354
 355     yield
 356     yield from print_reg(dut, [3,4,5])
 357     yield
 358     yield from print_reg(dut, [3,4,5])
 359     yield
 360     yield
 361     yield
 362     yield
 363     yield from alusim.check(dut)
 364
 365
 366 def explore_groups(dut):
 367     from nmigen.hdl.ir import Fragment
 368     from nmigen.hdl.xfrm import LHSGroupAnalyzer
 369
 370     fragment = dut.elaborate(platform=None)
 371     fr = Fragment.get(fragment, platform=None)
 372
 373     groups = LHSGroupAnalyzer()(fragment._statements)
 374
 375     print (groups)
 376
 377
 378 def test_scoreboard():
 379     dut = Scoreboard(32, 8)
 380     alusim = RegSim(32, 8)
 381     vl = rtlil.convert(dut, ports=dut.ports())
 382     with open("test_scoreboard6600.il", "w") as f:
 383         f.write(vl)
 384
 385     run_simulation(dut, scoreboard_sim(dut, alusim),
 386                         vcd_name='test_scoreboard6600.vcd')
 387
 388
 389 if __name__ == '__main__':
 390     test_scoreboard()