src/scoreboard/fu_reg_matrix.py

   1 from nmigen.compat.sim import run_simulation
   2 from nmigen.cli import verilog, rtlil
   3 from nmigen import Module, Signal, Elaboratable, Array, Cat
   4
   5 from scoreboard.dependence_cell import DependencyRow
   6 from scoreboard.fu_wr_pending import FU_RW_Pend
   7 from scoreboard.reg_select import Reg_Rsv
   8 from scoreboard.global_pending import GlobalPending
   9
  10 """
  11
  12  6600 Dependency Table Matrix inputs / outputs
  13  ---------------------------------------------
  14
  15                 d s1 s2 i  d s1 s2 i  d s1 s2 i  d s1 s2 i
  16                 | |   | |  | |   | |  | |   | |  | |   | |
  17                 v v   v v  v v   v v  v v   v v  v v   v v
  18  go_rd/go_wr -> dm-r0-fu0  dm-r1-fu0  dm-r2-fu0  dm-r3-fu0 -> wr/rd-pend
  19  go_rd/go_wr -> dm-r0-fu1  dm-r1-fu1  dm-r2-fu1  dm-r3-fu1 -> wr/rd-pend
  20  go_rd/go_wr -> dm-r0-fu2  dm-r1-fu2  dm-r2-fu2  dm-r3-fu2 -> wr/rd-pend
  21                  |  |  |    |  |  |    |  |  |    |  |  |
  22                  v  v  v    v  v  v    v  v  v    v  v  v
  23                  d  s1 s2   d  s1 s2   d  s1 s2   d  s1 s2
  24                  reg sel    reg sel    reg sel    reg sel
  25
  26 """
  27
  28 class FURegDepMatrix(Elaboratable):
  29     """ implements 11.4.7 mitch alsup FU-to-Reg Dependency Matrix, p26
  30     """
  31     def __init__(self, n_fu_row, n_reg_col):
  32         self.n_fu_row = n_fu_row                  # Y (FUs)   ^v
  33         self.n_reg_col = n_reg_col                # X (Regs)  <>
  34         self.dest_i = Signal(n_reg_col, reset_less=True)     # Dest in (top)
  35         self.src1_i = Signal(n_reg_col, reset_less=True)     # oper1 in (top)
  36         self.src2_i = Signal(n_reg_col, reset_less=True)     # oper2 in (top)
  37
  38         # Register "Global" vectors for determining RaW and WaR hazards
  39         self.wr_pend_i = Signal(n_reg_col, reset_less=True) # wr pending (top)
  40         self.rd_pend_i = Signal(n_reg_col, reset_less=True) # rd pending (top)
  41         self.v_wr_rsel_o = Signal(n_reg_col, reset_less=True) # wr pending (bot)
  42         self.v_rd_rsel_o = Signal(n_reg_col, reset_less=True) # rd pending (bot)
  43
  44         self.issue_i = Signal(n_fu_row, reset_less=True)  # Issue in (top)
  45         self.go_wr_i = Signal(n_fu_row, reset_less=True)  # Go Write in (left)
  46         self.go_rd_i = Signal(n_fu_row, reset_less=True)  # Go Read in (left)
  47         self.go_die_i = Signal(n_fu_row, reset_less=True) # Go Die in (left)
  48
  49         # for Register File Select Lines (horizontal), per-reg
  50         self.dest_rsel_o = Signal(n_reg_col, reset_less=True) # dest reg (bot)
  51         self.src1_rsel_o = Signal(n_reg_col, reset_less=True) # src1 reg (bot)
  52         self.src2_rsel_o = Signal(n_reg_col, reset_less=True) # src2 reg (bot)
  53
  54         # for Function Unit "forward progress" (vertical), per-FU
  55         self.wr_pend_o = Signal(n_fu_row, reset_less=True) # wr pending (right)
  56         self.rd_pend_o = Signal(n_fu_row, reset_less=True) # rd pending (right)
  57         self.rd_src1_pend_o = Signal(n_fu_row, reset_less=True) # src1 pending
  58         self.rd_src2_pend_o = Signal(n_fu_row, reset_less=True) # src2 pending
  59
  60     def elaborate(self, platform):
  61         m = Module()
  62
  63         # ---
  64         # matrix of dependency cells
  65         # ---
  66         dm = Array(DependencyRow(self.n_reg_col) for r in range(self.n_fu_row))
  67         for fu in range(self.n_fu_row):
  68             setattr(m.submodules, "dr_fu%d" % fu, dm[fu])
  69
  70         # ---
  71         # array of Function Unit Pending vectors
  72         # ---
  73         fupend = Array(FU_RW_Pend(self.n_reg_col) for f in range(self.n_fu_row))
  74         for fu in range(self.n_fu_row):
  75             setattr(m.submodules, "fu_fu%d" % (fu), fupend[fu])
  76
  77         # ---
  78         # array of Register Reservation vectors
  79         # ---
  80         regrsv = Array(Reg_Rsv(self.n_fu_row) for r in range(self.n_reg_col))
  81         for rn in range(self.n_reg_col):
  82             setattr(m.submodules, "rr_r%d" % (rn), regrsv[rn])
  83
  84         # ---
  85         # connect Function Unit vector
  86         # ---
  87         wr_pend = []
  88         rd_pend = []
  89         rd_src1_pend = []
  90         rd_src2_pend = []
  91         for fu in range(self.n_fu_row):
  92             dc = dm[fu]
  93             fup = fupend[fu]
  94             dest_fwd_o = []
  95             src1_fwd_o = []
  96             src2_fwd_o = []
  97             for rn in range(self.n_reg_col):
  98                 # accumulate cell fwd outputs for dest/src1/src2
  99                 dest_fwd_o.append(dc.dest_fwd_o[rn])
 100                 src1_fwd_o.append(dc.src1_fwd_o[rn])
 101                 src2_fwd_o.append(dc.src2_fwd_o[rn])
 102             # connect cell fwd outputs to FU Vector in [Cat is gooood]
 103             m.d.comb += [fup.dest_fwd_i.eq(Cat(*dest_fwd_o)),
 104                          fup.src1_fwd_i.eq(Cat(*src1_fwd_o)),
 105                          fup.src2_fwd_i.eq(Cat(*src2_fwd_o))
 106                         ]
 107             # accumulate FU Vector outputs
 108             wr_pend.append(fup.reg_wr_pend_o)
 109             rd_pend.append(fup.reg_rd_pend_o)
 110             rd_src1_pend.append(fup.reg_rd_src1_pend_o)
 111             rd_src2_pend.append(fup.reg_rd_src2_pend_o)
 112
 113         # ... and output them from this module (vertical, width=FUs)
 114         m.d.comb += self.wr_pend_o.eq(Cat(*wr_pend))
 115         m.d.comb += self.rd_pend_o.eq(Cat(*rd_pend))
 116         m.d.comb += self.rd_src1_pend_o.eq(Cat(*rd_src1_pend))
 117         m.d.comb += self.rd_src2_pend_o.eq(Cat(*rd_src2_pend))
 118
 119         # ---
 120         # connect Reg Selection vector
 121         # ---
 122         dest_rsel = []
 123         src1_rsel = []
 124         src2_rsel = []
 125         for rn in range(self.n_reg_col):
 126             rsv = regrsv[rn]
 127             dest_rsel_o = []
 128             src1_rsel_o = []
 129             src2_rsel_o = []
 130             for fu in range(self.n_fu_row):
 131                 dc = dm[fu]
 132                 # accumulate cell reg-select outputs dest/src1/src2
 133                 dest_rsel_o.append(dc.dest_rsel_o[rn])
 134                 src1_rsel_o.append(dc.src1_rsel_o[rn])
 135                 src2_rsel_o.append(dc.src2_rsel_o[rn])
 136             # connect cell reg-select outputs to Reg Vector In
 137             m.d.comb += [rsv.dest_rsel_i.eq(Cat(*dest_rsel_o)),
 138                          rsv.src1_rsel_i.eq(Cat(*src1_rsel_o)),
 139                          rsv.src2_rsel_i.eq(Cat(*src2_rsel_o)),
 140                         ]
 141             # accumulate Reg-Sel Vector outputs
 142             dest_rsel.append(rsv.dest_rsel_o)
 143             src1_rsel.append(rsv.src1_rsel_o)
 144             src2_rsel.append(rsv.src2_rsel_o)
 145
 146         # ... and output them from this module (horizontal, width=REGs)
 147         m.d.comb += self.dest_rsel_o.eq(Cat(*dest_rsel))
 148         m.d.comb += self.src1_rsel_o.eq(Cat(*src1_rsel))
 149         m.d.comb += self.src2_rsel_o.eq(Cat(*src2_rsel))
 150
 151         # ---
 152         # connect Dependency Matrix dest/src1/src2/issue to module d/s/s/i
 153         # ---
 154         for fu in range(self.n_fu_row):
 155             dc = dm[fu]
 156             # wire up inputs from module to row cell inputs (Cat is gooood)
 157             m.d.comb += [dc.dest_i.eq(self.dest_i),
 158                          dc.src1_i.eq(self.src1_i),
 159                          dc.src2_i.eq(self.src2_i),
 160                          dc.rd_pend_i.eq(self.rd_pend_i),
 161                          dc.wr_pend_i.eq(self.wr_pend_i),
 162                         ]
 163
 164         # accumulate rsel bits into read/write pending vectors.
 165         rd_pend_v = []
 166         wr_pend_v = []
 167         for fu in range(self.n_fu_row):
 168             dc = dm[fu]
 169             rd_pend_v.append(dc.v_rd_rsel_o)
 170             wr_pend_v.append(dc.v_wr_rsel_o)
 171         rd_v = GlobalPending(self.n_reg_col, rd_pend_v)
 172         wr_v = GlobalPending(self.n_reg_col, wr_pend_v)
 173         m.submodules.rd_v = rd_v
 174         m.submodules.wr_v = wr_v
 175
 176         m.d.comb += self.v_rd_rsel_o.eq(rd_v.g_pend_o)
 177         m.d.comb += self.v_wr_rsel_o.eq(wr_v.g_pend_o)
 178
 179         # ---
 180         # connect Dep issue_i/go_rd_i/go_wr_i to module issue_i/go_rd/go_wr
 181         # ---
 182         go_rd_i = []
 183         go_wr_i = []
 184         go_die_i = []
 185         issue_i = []
 186         for fu in range(self.n_fu_row):
 187             dc = dm[fu]
 188             # accumulate cell fwd outputs for dest/src1/src2
 189             go_rd_i.append(dc.go_rd_i)
 190             go_wr_i.append(dc.go_wr_i)
 191             go_die_i.append(dc.go_die_i)
 192             issue_i.append(dc.issue_i)
 193         # wire up inputs from module to row cell inputs (Cat is gooood)
 194         m.d.comb += [Cat(*go_rd_i).eq(self.go_rd_i),
 195                      Cat(*go_wr_i).eq(self.go_wr_i),
 196                      Cat(*go_die_i).eq(self.go_die_i),
 197                      Cat(*issue_i).eq(self.issue_i),
 198                     ]
 199
 200         return m
 201
 202     def __iter__(self):
 203         yield self.dest_i
 204         yield self.src1_i
 205         yield self.src2_i
 206         yield self.issue_i
 207         yield self.go_wr_i
 208         yield self.go_rd_i
 209         yield self.go_die_i
 210         yield self.dest_rsel_o
 211         yield self.src1_rsel_o
 212         yield self.src2_rsel_o
 213         yield self.wr_pend_o
 214         yield self.rd_pend_o
 215         yield self.wr_pend_i
 216         yield self.rd_pend_i
 217         yield self.v_wr_rsel_o
 218         yield self.v_rd_rsel_o
 219         yield self.rd_src1_pend_o
 220         yield self.rd_src2_pend_o
 221
 222     def ports(self):
 223         return list(self)
 224
 225 def d_matrix_sim(dut):
 226     """ XXX TODO
 227     """
 228     yield dut.dest_i.eq(1)
 229     yield dut.issue_i.eq(1)
 230     yield
 231     yield dut.issue_i.eq(0)
 232     yield
 233     yield dut.src1_i.eq(1)
 234     yield dut.issue_i.eq(1)
 235     yield
 236     yield dut.issue_i.eq(0)
 237     yield
 238     yield dut.go_rd_i.eq(1)
 239     yield
 240     yield dut.go_rd_i.eq(0)
 241     yield
 242     yield dut.go_wr_i.eq(1)
 243     yield
 244     yield dut.go_wr_i.eq(0)
 245     yield
 246
 247 def test_d_matrix():
 248     dut = FURegDepMatrix(n_fu_row=3, n_reg_col=4)
 249     vl = rtlil.convert(dut, ports=dut.ports())
 250     with open("test_fu_reg_matrix.il", "w") as f:
 251         f.write(vl)
 252
 253     run_simulation(dut, d_matrix_sim(dut), vcd_name='test_fu_reg_matrix.vcd')
 254
 255 if __name__ == '__main__':
 256     test_d_matrix()