src/soc/bus/syscon.py

   1 #!/usr/bin/env python3
   2 #
   3 # SPDX-License-Identifier: LGPLv3+
   4 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   5 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
   6 # Part of the Libre-SOC Project.
   7 #
   8 # this is a System Console peripheral compatible with microwatt
   9 # https://github.com/antonblanchard/microwatt/blob/master/syscon.vhdl
  10
  11 from nmigen import (Elaboratable, Cat, Module, Signal)
  12 from nmigen.cli import rtlil, verilog
  13
  14 from lambdasoc.periph import Peripheral
  15
  16 __all__ = ["MicrowattSYSCON"]
  17
  18
  19 class MicrowattSYSCON(Peripheral, Elaboratable):
  20     """Microwatt-compatible (Sys)tem (Con)figuration module
  21     """
  22
  23     def __init__(self, *, sys_clk_freq=100e6,
  24                           spi_offset=None,
  25                           dram_addr=None,
  26                           has_uart=True,
  27                           uart_is_16550=True
  28                           ):
  29         super().__init__(name="syscon")
  30         self.sys_clk_freq = sys_clk_freq
  31         self.has_uart = has_uart
  32         self.spi_offset = spi_offset
  33         self.dram_addr = dram_addr
  34         self.uart_is_16550 = uart_is_16550
  35
  36         # System control ports
  37         self.dram_at_0 = Signal()
  38         self.core_reset = Signal()
  39         self.soc_reset = Signal()
  40
  41         # set up a CSR Bank and associated bridge. has to be in this order
  42         # (declare bank, declare bridge) for some unknown reason.
  43         # (r)ead regs will have a r_stb and r_data Record entry
  44         # (w)rite regs will have a w_stb and w_data Record entry
  45         bank = self.csr_bank()
  46         self._reg_sig_r       = bank.csr(64, "r") # signature
  47         self._reg_info_r      = bank.csr(64, "r") # info
  48         self._bram_info_r     = bank.csr(64, "r") # bram info
  49         self._dram_info_r     = bank.csr(64, "r") # dram info
  50         self._clk_info_r      = bank.csr(64, "r") # clock frequency
  51         self._ctrl_info_r     = bank.csr(64, "rw") # control info
  52         self._dram_init_r     = bank.csr(64, "r") # dram initialisation info
  53         self._spiflash_info_r = bank.csr(64, "r") # spi flash info
  54         self._uart0_info_r    = bank.csr(64, "r") # UART0 info (baud etc.)
  55         self._uart1_info_r    = bank.csr(64, "r") # UART1 info (baud etc.)
  56         self._bram_bootaddr_r = bank.csr(64, "r") # BRAM boot address
  57
  58         # bridge the above-created CSRs over wishbone.  ordering and size
  59         # above mattered, the bridge automatically packs them together
  60         # as memory-addressable "things" for us
  61         self._bridge = self.bridge(data_width=32, granularity=8, alignment=3)
  62         self.bus = self._bridge.bus
  63
  64     def elaborate(self, platform):
  65         m = Module()
  66         comb, sync = m.d.comb, m.d.comb
  67         m.submodules.bridge = self._bridge
  68
  69         # enter data into the CSRs. r_data can be left live all the time,
  70         # w_data obviously has to be set only when w_stb triggers.
  71
  72         # identifying signature
  73         comb += self._reg_sig_r.r_data.eq(0xf00daa5500010001)
  74
  75         # system clock rate (hz)
  76         comb += self._clk_info_r.r_data.eq(int(self.sys_clk_freq)) # in hz
  77
  78         # detect peripherals
  79         has_spi = self.spi_offset is not None
  80         has_dram = self.dram_addr is not None
  81
  82         # uart peripheral clock rate, currently assumed to be system clock
  83         # 0 ..31  : UART clock freq (in HZ)
  84         #     32  : UART is 16550 (otherwise pp)
  85         comb += self._uart0_info_r.r_data[0:32].eq(int(self.sys_clk_freq))
  86         comb += self._uart0_info_r.r_data[32].eq(1)
  87
  88         # Reg Info, defines what peripherals and characteristics are present
  89         comb += self._reg_info_r.r_data[0].eq(self.has_uart) # has UART0
  90         comb += self._reg_info_r.r_data[1].eq(has_dram)      # has DDR DRAM
  91         comb += self._reg_info_r.r_data[3].eq(has_spi)       # has SPI Flash
  92         comb += self._reg_info_r.r_data[5].eq(1)             # Large SYSCON
  93
  94         # system control
  95         sysctrl = Cat(self.dram_at_0, self.core_reset, self.soc_reset)
  96         with m.If(self._ctrl_info_r.w_stb):
  97             sync += sysctrl.eq(self._ctrl_info_r.w_data)
  98         comb += self._ctrl_info_r.r_data.eq(sysctrl)
  99
 100         # SPI Flash Address
 101         comb += self._spiflash_info_r.r_data.eq(self.spi_offset or 0)
 102
 103         return m
 104
 105
 106 def create_ilang(dut, ports, test_name):
 107     vl = rtlil.convert(dut, name=test_name, ports=ports)
 108     with open("%s.il" % test_name, "w") as f:
 109         f.write(vl)
 110
 111 def create_verilog(dut, ports, test_name):
 112     vl = verilog.convert(dut, name=test_name, ports=ports)
 113     with open("%s.v" % test_name, "w") as f:
 114         f.write(vl)
 115
 116
 117 if __name__ == "__main__":
 118     from nmigen_soc import wishbone
 119     class QuickDemo(Elaboratable):
 120         def elaborate(self, platform):
 121             m = Module()
 122             arbiter = wishbone.Arbiter(addr_width=30, data_width=32,
 123                                        granularity=8)
 124             decoder = wishbone.Decoder(addr_width=30, data_width=32,
 125                                        granularity=8)
 126             m.submodules.syscon = syscon = MicrowattSYSCON()
 127             m.submodules.decoder = decoder
 128             m.submodules.arbiter = arbiter
 129             decoder.add(syscon.bus, addr=0xc0000000)
 130             m.d.comb += arbiter.bus.connect(decoder.bus)
 131             return m
 132     m = QuickDemo()
 133     create_ilang(m, None, "syscondemo")
 134