3 # SPDX-License-Identifier: LGPLv3+
4 # Copyright (C) 2022 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 # Sponsored by NLnet and NGI POINTER under EU Grants 871528 and 957073
6 # Part of the Libre-SOC Project.
8 # this is a System Console peripheral compatible with microwatt
9 # https://github.com/antonblanchard/microwatt/blob/master/syscon.vhdl
11 from nmigen
import (Elaboratable
, Cat
, Module
, Signal
)
12 from nmigen
.cli
import rtlil
, verilog
14 from lambdasoc
.periph
import Peripheral
16 __all__
= ["MicrowattSYSCON"]
19 class MicrowattSYSCON(Peripheral
, Elaboratable
):
20 """Microwatt-compatible (Sys)tem (Con)figuration module
23 def __init__(self
, *, sys_clk_freq
=100e6
,
28 super().__init
__(name
="syscon")
29 self
.sys_clk_freq
= sys_clk_freq
30 self
.has_uart
= has_uart
31 self
.spi_offset
= spi_offset
32 self
.uart_is_16550
= uart_is_16550
34 # System control ports
35 self
.dram_at_0
= Signal()
36 self
.core_reset
= Signal()
37 self
.soc_reset
= Signal()
39 # set up a CSR Bank and associated bridge. has to be in this order
40 # (declare bank, declare bridge) for some unknown reason.
41 # (r)ead regs will have a r_stb and r_data Record entry
42 # (w)rite regs will have a w_stb and w_data Record entry
43 bank
= self
.csr_bank()
44 self
._reg
_sig
_r
= bank
.csr(64, "r") # signature
45 self
._reg
_info
_r
= bank
.csr(64, "r") # info
46 self
._bram
_info
_r
= bank
.csr(64, "r") # bram info
47 self
._dram
_info
_r
= bank
.csr(64, "r") # dram info
48 self
._clk
_info
_r
= bank
.csr(64, "r") # clock frequency
49 self
._ctrl
_info
_r
= bank
.csr(64, "rw") # control info
50 self
._dram
_init
_r
= bank
.csr(64, "r") # dram initialisation info
51 self
._spiflash
_info
_r
= bank
.csr(64, "r") # spi flash info
52 self
._uart
0_info
_r
= bank
.csr(64, "r") # UART0 info (baud etc.)
53 self
._uart
1_info
_r
= bank
.csr(64, "r") # UART1 info (baud etc.)
54 self
._bram
_bootaddr
_r
= bank
.csr(64, "r") # BRAM boot address
56 # bridge the above-created CSRs over wishbone. ordering and size
57 # above mattered, the bridge automatically packs them together
58 # as memory-addressable "things" for us
59 self
._bridge
= self
.bridge(data_width
=32, granularity
=8, alignment
=3)
60 self
.bus
= self
._bridge
.bus
62 def elaborate(self
, platform
):
64 comb
, sync
= m
.d
.comb
, m
.d
.comb
65 m
.submodules
.bridge
= self
._bridge
67 # enter data into the CSRs. r_data can be left live all the time,
68 # w_data obviously has to be set only when w_stb triggers.
70 # identifying signature
71 comb
+= self
._reg
_sig
_r
.r_data
.eq(0xf00daa5500010001)
73 # system clock rate (hz)
74 comb
+= self
._clk
_info
_r
.r_data
.eq(int(self
.sys_clk_freq
)) # in hz
77 has_spi
= self
.spi_offset
is not None
79 # uart peripheral clock rate, currently assumed to be system clock
80 # 0 ..31 : UART clock freq (in HZ)
81 # 32 : UART is 16550 (otherwise pp)
82 comb
+= self
._uart
0_info
_r
.r_data
[0:32].eq(int(self
.sys_clk_freq
))
83 comb
+= self
._uart
0_info
_r
.r_data
[32].eq(1)
85 # Reg Info, defines what peripherals and characteristics are present
86 comb
+= self
._reg
_info
_r
.r_data
[0].eq(self
.has_uart
) # has UART0
87 comb
+= self
._reg
_info
_r
.r_data
[3].eq(has_spi
) # has SPI Flash
88 comb
+= self
._reg
_info
_r
.r_data
[5].eq(1) # Large SYSCON
91 sysctrl
= Cat(self
.dram_at_0
, self
.core_reset
, self
.soc_reset
)
92 with m
.If(self
._ctrl
_info
_r
.w_stb
):
93 sync
+= sysctrl
.eq(self
._ctrl
_info
_r
.w_data
)
94 comb
+= self
._ctrl
_info
_r
.r_data
.eq(sysctrl
)
97 comb
+= self
._spiflash
_info
_r
.r_data
.eq(self
.spi_offset
or 0)
102 def create_ilang(dut
, ports
, test_name
):
103 vl
= rtlil
.convert(dut
, name
=test_name
, ports
=ports
)
104 with
open("%s.il" % test_name
, "w") as f
:
107 def create_verilog(dut
, ports
, test_name
):
108 vl
= verilog
.convert(dut
, name
=test_name
, ports
=ports
)
109 with
open("%s.v" % test_name
, "w") as f
:
113 if __name__
== "__main__":
114 from nmigen_soc
import wishbone
115 class QuickDemo(Elaboratable
):
116 def elaborate(self
, platform
):
118 arbiter
= wishbone
.Arbiter(addr_width
=30, data_width
=32,
120 decoder
= wishbone
.Decoder(addr_width
=30, data_width
=32,
122 m
.submodules
.syscon
= syscon
= MicrowattSYSCON()
123 m
.submodules
.decoder
= decoder
124 m
.submodules
.arbiter
= arbiter
125 decoder
.add(syscon
.bus
, addr
=0xc0000000)
126 m
.d
.comb
+= arbiter
.bus
.connect(decoder
.bus
)
129 create_ilang(m
, None, "syscondemo")