1 """Wishbone read/write utility routines
5 def wb_write(bus
, addr
, data
, sel
=0b1111):
11 #yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
13 yield bus
.adr
.eq(addr
)
14 yield bus
.dat_w
.eq(data
)
16 # wait for ack to go high
22 yield # loop until ack
23 yield bus
.stb
.eq(0) # drop stb so only 1 thing into pipeline
25 # leave cyc/stb valid for 1 cycle while writing
28 # clear out before returning data
37 def wb_read(bus
, addr
, sel
=0b1111):
43 #yield bus.sel.eq(0b1111 if sel else 0b1) # 32-bit / 8-bit
45 yield bus
.adr
.eq(addr
)
47 # wait for ack to go high
53 yield # loop until ack
54 yield bus
.stb
.eq(0) # drop stb so only 1 thing into pipeline
56 # get data on same cycle that ack raises
57 data
= yield bus
.dat_r
59 # leave cyc/stb valid for 1 cycle while reading
62 # clear out before returning data