src/soc/decoder/power_decoder2.py

   1 """Power ISA Decoder second stage
   2
   3 based on Anton Blanchard microwatt decode2.vhdl
   4
   5 Note: OP_TRAP is used for exceptions and interrupts (micro-code style) by
   6 over-riding the internal opcode when an exception is needed.
   7 """
   8
   9 from nmigen import Module, Elaboratable, Signal, Mux, Const, Cat, Repl, Record
  10 from nmigen.cli import rtlil
  11 from soc.regfile.regfiles import XERRegs
  12
  13 from nmutil.picker import PriorityPicker
  14 from nmutil.iocontrol import RecordObject
  15 from nmutil.extend import exts
  16
  17 from soc.decoder.power_regspec_map import regspec_decode_read
  18 from soc.decoder.power_regspec_map import regspec_decode_write
  19 from soc.decoder.power_decoder import create_pdecode
  20 from soc.decoder.power_enums import (MicrOp, CryIn, Function,
  21                                      CRInSel, CROutSel,
  22                                      LdstLen, In1Sel, In2Sel, In3Sel,
  23                                      OutSel, SPR, RC, LDSTMode)
  24 from soc.decoder.decode2execute1 import Decode2ToExecute1Type, Data
  25 from soc.consts import MSR
  26
  27 from soc.regfile.regfiles import FastRegs
  28 from soc.consts import TT
  29 from soc.config.state import CoreState
  30
  31
  32 def decode_spr_num(spr):
  33     return Cat(spr[5:10], spr[0:5])
  34
  35
  36 def instr_is_priv(m, op, insn):
  37     """determines if the instruction is privileged or not
  38     """
  39     comb = m.d.comb
  40     is_priv_insn = Signal(reset_less=True)
  41     with m.Switch(op):
  42         with m.Case(MicrOp.OP_ATTN, MicrOp.OP_MFMSR, MicrOp.OP_MTMSRD,
  43                     MicrOp.OP_MTMSR, MicrOp.OP_RFID):
  44             comb += is_priv_insn.eq(1)
  45         # XXX TODO
  46         #with m.Case(MicrOp.OP_TLBIE) : comb += is_priv_insn.eq(1)
  47         with m.Case(MicrOp.OP_MFSPR, MicrOp.OP_MTSPR):
  48             with m.If(insn[20]):  # field XFX.spr[-1] i think
  49                 comb += is_priv_insn.eq(1)
  50     return is_priv_insn
  51
  52
  53 class SPRMap(Elaboratable):
  54     """SPRMap: maps POWER9 SPR numbers to internal enum values
  55     """
  56
  57     def __init__(self):
  58         self.spr_i = Signal(10, reset_less=True)
  59         self.spr_o = Signal(SPR, reset_less=True)
  60
  61     def elaborate(self, platform):
  62         m = Module()
  63         with m.Switch(self.spr_i):
  64             for i, x in enumerate(SPR):
  65                 with m.Case(x.value):
  66                     m.d.comb += self.spr_o.eq(i)
  67         return m
  68
  69
  70 class DecodeA(Elaboratable):
  71     """DecodeA from instruction
  72
  73     decodes register RA, whether immediate-zero, implicit and
  74     explicit CSRs
  75     """
  76
  77     def __init__(self, dec):
  78         self.dec = dec
  79         self.sel_in = Signal(In1Sel, reset_less=True)
  80         self.insn_in = Signal(32, reset_less=True)
  81         self.reg_out = Data(5, name="reg_a")
  82         self.immz_out = Signal(reset_less=True)
  83         self.spr_out = Data(SPR, "spr_a")
  84         self.fast_out = Data(3, "fast_a")
  85
  86     def elaborate(self, platform):
  87         m = Module()
  88         comb = m.d.comb
  89         m.submodules.sprmap = sprmap = SPRMap()
  90
  91         # select Register A field
  92         ra = Signal(5, reset_less=True)
  93         comb += ra.eq(self.dec.RA)
  94         with m.If((self.sel_in == In1Sel.RA) |
  95                   ((self.sel_in == In1Sel.RA_OR_ZERO) &
  96                    (ra != Const(0, 5)))):
  97             comb += self.reg_out.data.eq(ra)
  98             comb += self.reg_out.ok.eq(1)
  99
 100         # zero immediate requested
 101         with m.If((self.sel_in == In1Sel.RA_OR_ZERO) &
 102                   (self.reg_out.data == Const(0, 5))):
 103             comb += self.immz_out.eq(1)
 104
 105         # some Logic/ALU ops have RS as the 3rd arg, but no "RA".
 106         with m.If(self.sel_in == In1Sel.RS):
 107             comb += self.reg_out.data.eq(self.dec.RS)
 108             comb += self.reg_out.ok.eq(1)
 109
 110         # decode Fast-SPR based on instruction type
 111         op = self.dec.op
 112         with m.Switch(op.internal_op):
 113
 114             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeOut
 115             with m.Case(MicrOp.OP_BC):
 116                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 117                     # constant: CTR
 118                     comb += self.fast_out.data.eq(FastRegs.CTR)
 119                     comb += self.fast_out.ok.eq(1)
 120             with m.Case(MicrOp.OP_BCREG):
 121                 xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 122                 xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 123                 with m.If(xo9 & ~xo5):
 124                     # constant: CTR
 125                     comb += self.fast_out.data.eq(FastRegs.CTR)
 126                     comb += self.fast_out.ok.eq(1)
 127
 128             # MFSPR move from SPRs
 129             with m.Case(MicrOp.OP_MFSPR):
 130                 spr = Signal(10, reset_less=True)
 131                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 132                 with m.Switch(spr):
 133                     # fast SPRs
 134                     with m.Case(SPR.CTR.value):
 135                         comb += self.fast_out.data.eq(FastRegs.CTR)
 136                         comb += self.fast_out.ok.eq(1)
 137                     with m.Case(SPR.LR.value):
 138                         comb += self.fast_out.data.eq(FastRegs.LR)
 139                         comb += self.fast_out.ok.eq(1)
 140                     with m.Case(SPR.TAR.value):
 141                         comb += self.fast_out.data.eq(FastRegs.TAR)
 142                         comb += self.fast_out.ok.eq(1)
 143                     with m.Case(SPR.SRR0.value):
 144                         comb += self.fast_out.data.eq(FastRegs.SRR0)
 145                         comb += self.fast_out.ok.eq(1)
 146                     with m.Case(SPR.SRR1.value):
 147                         comb += self.fast_out.data.eq(FastRegs.SRR1)
 148                         comb += self.fast_out.ok.eq(1)
 149                     with m.Case(SPR.XER.value):
 150                         pass  # do nothing
 151                     # : map to internal SPR numbers
 152                     # XXX TODO: dec and tb not to go through mapping.
 153                     with m.Default():
 154                         comb += sprmap.spr_i.eq(spr)
 155                         comb += self.spr_out.data.eq(sprmap.spr_o)
 156                         comb += self.spr_out.ok.eq(1)
 157
 158         return m
 159
 160
 161 class DecodeB(Elaboratable):
 162     """DecodeB from instruction
 163
 164     decodes register RB, different forms of immediate (signed, unsigned),
 165     and implicit SPRs.  register B is basically "lane 2" into the CompUnits.
 166     by industry-standard convention, "lane 2" is where fully-decoded
 167     immediates are muxed in.
 168     """
 169
 170     def __init__(self, dec):
 171         self.dec = dec
 172         self.sel_in = Signal(In2Sel, reset_less=True)
 173         self.insn_in = Signal(32, reset_less=True)
 174         self.reg_out = Data(5, "reg_b")
 175         self.imm_out = Data(64, "imm_b")
 176         self.fast_out = Data(3, "fast_b")
 177
 178     def elaborate(self, platform):
 179         m = Module()
 180         comb = m.d.comb
 181
 182         # select Register B field
 183         with m.Switch(self.sel_in):
 184             with m.Case(In2Sel.RB):
 185                 comb += self.reg_out.data.eq(self.dec.RB)
 186                 comb += self.reg_out.ok.eq(1)
 187             with m.Case(In2Sel.RS):
 188                 # for M-Form shiftrot
 189                 comb += self.reg_out.data.eq(self.dec.RS)
 190                 comb += self.reg_out.ok.eq(1)
 191             with m.Case(In2Sel.CONST_UI): # unsigned
 192                 comb += self.imm_out.data.eq(self.dec.UI)
 193                 comb += self.imm_out.ok.eq(1)
 194             with m.Case(In2Sel.CONST_SI):  # sign-extended 16-bit
 195                 si = Signal(16, reset_less=True)
 196                 comb += si.eq(self.dec.SI)
 197                 comb += self.imm_out.data.eq(exts(si, 16, 64))
 198                 comb += self.imm_out.ok.eq(1)
 199             with m.Case(In2Sel.CONST_SI_HI):  # sign-extended 16+16=32 bit
 200                 si_hi = Signal(32, reset_less=True)
 201                 comb += si_hi.eq(self.dec.SI << 16)
 202                 comb += self.imm_out.data.eq(exts(si_hi, 32, 64))
 203                 comb += self.imm_out.ok.eq(1)
 204             with m.Case(In2Sel.CONST_UI_HI): # unsigned
 205                 ui = Signal(16, reset_less=True)
 206                 comb += ui.eq(self.dec.UI)
 207                 comb += self.imm_out.data.eq(ui << 16)
 208                 comb += self.imm_out.ok.eq(1)
 209             with m.Case(In2Sel.CONST_LI): # sign-extend 24+2=26 bit
 210                 li = Signal(26, reset_less=True)
 211                 comb += li.eq(self.dec.LI << 2)
 212                 comb += self.imm_out.data.eq(exts(li, 26, 64))
 213                 comb += self.imm_out.ok.eq(1)
 214             with m.Case(In2Sel.CONST_BD): # sign-extend (14+2)=16 bit
 215                 bd = Signal(16, reset_less=True)
 216                 comb += bd.eq(self.dec.BD << 2)
 217                 comb += self.imm_out.data.eq(exts(bd, 16, 64))
 218                 comb += self.imm_out.ok.eq(1)
 219             with m.Case(In2Sel.CONST_DS): # sign-extended (14+2=16) bit
 220                 ds = Signal(16, reset_less=True)
 221                 comb += ds.eq(self.dec.DS << 2)
 222                 comb += self.imm_out.data.eq(exts(ds, 16, 64))
 223                 comb += self.imm_out.ok.eq(1)
 224             with m.Case(In2Sel.CONST_M1): # signed (-1)
 225                 comb += self.imm_out.data.eq(~Const(0, 64))  # all 1s
 226                 comb += self.imm_out.ok.eq(1)
 227             with m.Case(In2Sel.CONST_SH): # unsigned - for shift
 228                 comb += self.imm_out.data.eq(self.dec.sh)
 229                 comb += self.imm_out.ok.eq(1)
 230             with m.Case(In2Sel.CONST_SH32): # unsigned - for shift
 231                 comb += self.imm_out.data.eq(self.dec.SH32)
 232                 comb += self.imm_out.ok.eq(1)
 233
 234         # decode SPR2 based on instruction type
 235         op = self.dec.op
 236         # BCREG implicitly uses LR or TAR for 2nd reg
 237         # CTR however is already in fast_spr1 *not* 2.
 238         with m.If(op.internal_op == MicrOp.OP_BCREG):
 239             xo9 = self.dec.FormXL.XO[9]  # 3.0B p38 top bit of XO
 240             xo5 = self.dec.FormXL.XO[5]  # 3.0B p38
 241             with m.If(~xo9):
 242                 comb += self.fast_out.data.eq(FastRegs.LR)
 243                 comb += self.fast_out.ok.eq(1)
 244             with m.Elif(xo5):
 245                 comb += self.fast_out.data.eq(FastRegs.TAR)
 246                 comb += self.fast_out.ok.eq(1)
 247
 248         return m
 249
 250
 251 class DecodeC(Elaboratable):
 252     """DecodeC from instruction
 253
 254     decodes register RC.  this is "lane 3" into some CompUnits (not many)
 255     """
 256
 257     def __init__(self, dec):
 258         self.dec = dec
 259         self.sel_in = Signal(In3Sel, reset_less=True)
 260         self.insn_in = Signal(32, reset_less=True)
 261         self.reg_out = Data(5, "reg_c")
 262
 263     def elaborate(self, platform):
 264         m = Module()
 265         comb = m.d.comb
 266
 267         # select Register C field
 268         with m.Switch(self.sel_in):
 269             with m.Case(In3Sel.RB):
 270                 # for M-Form shiftrot
 271                 comb += self.reg_out.data.eq(self.dec.RB)
 272                 comb += self.reg_out.ok.eq(1)
 273             with m.Case(In3Sel.RS):
 274                 comb += self.reg_out.data.eq(self.dec.RS)
 275                 comb += self.reg_out.ok.eq(1)
 276
 277         return m
 278
 279
 280 class DecodeOut(Elaboratable):
 281     """DecodeOut from instruction
 282
 283     decodes output register RA, RT or SPR
 284     """
 285
 286     def __init__(self, dec):
 287         self.dec = dec
 288         self.sel_in = Signal(OutSel, reset_less=True)
 289         self.insn_in = Signal(32, reset_less=True)
 290         self.reg_out = Data(5, "reg_o")
 291         self.spr_out = Data(SPR, "spr_o")
 292         self.fast_out = Data(3, "fast_o")
 293
 294     def elaborate(self, platform):
 295         m = Module()
 296         comb = m.d.comb
 297         m.submodules.sprmap = sprmap = SPRMap()
 298         op = self.dec.op
 299
 300         # select Register out field
 301         with m.Switch(self.sel_in):
 302             with m.Case(OutSel.RT):
 303                 comb += self.reg_out.data.eq(self.dec.RT)
 304                 comb += self.reg_out.ok.eq(1)
 305             with m.Case(OutSel.RA):
 306                 comb += self.reg_out.data.eq(self.dec.RA)
 307                 comb += self.reg_out.ok.eq(1)
 308             with m.Case(OutSel.SPR):
 309                 spr = Signal(10, reset_less=True)
 310                 comb += spr.eq(decode_spr_num(self.dec.SPR))  # from XFX
 311                 # TODO MTSPR 1st spr (fast)
 312                 with m.If(op.internal_op == MicrOp.OP_MTSPR):
 313                     with m.Switch(spr):
 314                         # fast SPRs
 315                         with m.Case(SPR.CTR.value):
 316                             comb += self.fast_out.data.eq(FastRegs.CTR)
 317                             comb += self.fast_out.ok.eq(1)
 318                         with m.Case(SPR.LR.value):
 319                             comb += self.fast_out.data.eq(FastRegs.LR)
 320                             comb += self.fast_out.ok.eq(1)
 321                         with m.Case(SPR.TAR.value):
 322                             comb += self.fast_out.data.eq(FastRegs.TAR)
 323                             comb += self.fast_out.ok.eq(1)
 324                         with m.Case(SPR.SRR0.value):
 325                             comb += self.fast_out.data.eq(FastRegs.SRR0)
 326                             comb += self.fast_out.ok.eq(1)
 327                         with m.Case(SPR.SRR1.value):
 328                             comb += self.fast_out.data.eq(FastRegs.SRR1)
 329                             comb += self.fast_out.ok.eq(1)
 330                         with m.Case(SPR.XER.value):
 331                             pass  # do nothing
 332                         # : map to internal SPR numbers
 333                         # XXX TODO: dec and tb not to go through mapping.
 334                         with m.Default():
 335                             comb += sprmap.spr_i.eq(spr)
 336                             comb += self.spr_out.data.eq(sprmap.spr_o)
 337                             comb += self.spr_out.ok.eq(1)
 338
 339         with m.Switch(op.internal_op):
 340
 341             # BC or BCREG: implicit register (CTR) NOTE: same in DecodeA
 342             with m.Case(MicrOp.OP_BC, MicrOp.OP_BCREG):
 343                 with m.If(~self.dec.BO[2]):  # 3.0B p38 BO2=0, use CTR reg
 344                     # constant: CTR
 345                     comb += self.fast_out.data.eq(FastRegs.CTR)
 346                     comb += self.fast_out.ok.eq(1)
 347
 348             # RFID 1st spr (fast)
 349             with m.Case(MicrOp.OP_RFID):
 350                 comb += self.fast_out.data.eq(FastRegs.SRR0)  # constant: SRR0
 351                 comb += self.fast_out.ok.eq(1)
 352
 353         return m
 354
 355
 356 class DecodeOut2(Elaboratable):
 357     """DecodeOut2 from instruction
 358
 359     decodes output registers
 360     """
 361
 362     def __init__(self, dec):
 363         self.dec = dec
 364         self.sel_in = Signal(OutSel, reset_less=True)
 365         self.lk = Signal(reset_less=True)
 366         self.insn_in = Signal(32, reset_less=True)
 367         self.reg_out = Data(5, "reg_o")
 368         self.fast_out = Data(3, "fast_o")
 369
 370     def elaborate(self, platform):
 371         m = Module()
 372         comb = m.d.comb
 373
 374         # update mode LD/ST uses read-reg A also as an output
 375         with m.If(self.dec.op.upd == LDSTMode.update):
 376             comb += self.reg_out.eq(self.dec.RA)
 377             comb += self.reg_out.ok.eq(1)
 378
 379         # B, BC or BCREG: potential implicit register (LR) output
 380         # these give bl, bcl, bclrl, etc.
 381         op = self.dec.op
 382         with m.Switch(op.internal_op):
 383
 384             # BC* implicit register (LR)
 385             with m.Case(MicrOp.OP_BC, MicrOp.OP_B, MicrOp.OP_BCREG):
 386                 with m.If(self.lk):  # "link" mode
 387                     comb += self.fast_out.data.eq(FastRegs.LR)  # constant: LR
 388                     comb += self.fast_out.ok.eq(1)
 389
 390             # RFID 2nd spr (fast)
 391             with m.Case(MicrOp.OP_RFID):
 392                 comb += self.fast_out.data.eq(FastRegs.SRR1)  # constant: SRR1
 393                 comb += self.fast_out.ok.eq(1)
 394
 395         return m
 396
 397
 398 class DecodeRC(Elaboratable):
 399     """DecodeRc from instruction
 400
 401     decodes Record bit Rc
 402     """
 403
 404     def __init__(self, dec):
 405         self.dec = dec
 406         self.sel_in = Signal(RC, reset_less=True)
 407         self.insn_in = Signal(32, reset_less=True)
 408         self.rc_out = Data(1, "rc")
 409
 410     def elaborate(self, platform):
 411         m = Module()
 412         comb = m.d.comb
 413
 414         # select Record bit out field
 415         with m.Switch(self.sel_in):
 416             with m.Case(RC.RC):
 417                 comb += self.rc_out.data.eq(self.dec.Rc)
 418                 comb += self.rc_out.ok.eq(1)
 419             with m.Case(RC.ONE):
 420                 comb += self.rc_out.data.eq(1)
 421                 comb += self.rc_out.ok.eq(1)
 422             with m.Case(RC.NONE):
 423                 comb += self.rc_out.data.eq(0)
 424                 comb += self.rc_out.ok.eq(1)
 425
 426         return m
 427
 428
 429 class DecodeOE(Elaboratable):
 430     """DecodeOE from instruction
 431
 432     decodes OE field: uses RC decode detection which might not be good
 433
 434     -- For now, use "rc" in the decode table to decide whether oe exists.
 435     -- This is not entirely correct architecturally: For mulhd and
 436     -- mulhdu, the OE field is reserved. It remains to be seen what an
 437     -- actual POWER9 does if we set it on those instructions, for now we
 438     -- test that further down when assigning to the multiplier oe input.
 439     """
 440
 441     def __init__(self, dec):
 442         self.dec = dec
 443         self.sel_in = Signal(RC, reset_less=True)
 444         self.insn_in = Signal(32, reset_less=True)
 445         self.oe_out = Data(1, "oe")
 446
 447     def elaborate(self, platform):
 448         m = Module()
 449         comb = m.d.comb
 450         op = self.dec.op
 451
 452         with m.Switch(op.internal_op):
 453
 454             # mulhw, mulhwu, mulhd, mulhdu - these *ignore* OE
 455             # also rotate
 456             # XXX ARGH! ignoring OE causes incompatibility with microwatt
 457             # http://lists.libre-soc.org/pipermail/libre-soc-dev/2020-August/000302.html
 458             with m.Case(MicrOp.OP_MUL_H64, MicrOp.OP_MUL_H32,
 459                         MicrOp.OP_EXTS, MicrOp.OP_CNTZ,
 460                         MicrOp.OP_SHL, MicrOp.OP_SHR, MicrOp.OP_RLC,
 461                         MicrOp.OP_LOAD, MicrOp.OP_STORE,
 462                         MicrOp.OP_RLCL, MicrOp.OP_RLCR,
 463                         MicrOp.OP_EXTSWSLI):
 464                 pass
 465
 466             # all other ops decode OE field
 467             with m.Default():
 468                 # select OE bit out field
 469                 with m.Switch(self.sel_in):
 470                     with m.Case(RC.RC):
 471                         comb += self.oe_out.data.eq(self.dec.OE)
 472                         comb += self.oe_out.ok.eq(1)
 473
 474         return m
 475
 476
 477 class DecodeCRIn(Elaboratable):
 478     """Decodes input CR from instruction
 479
 480     CR indices - insn fields - (not the data *in* the CR) require only 3
 481     bits because they refer to CR0-CR7
 482     """
 483
 484     def __init__(self, dec):
 485         self.dec = dec
 486         self.sel_in = Signal(CRInSel, reset_less=True)
 487         self.insn_in = Signal(32, reset_less=True)
 488         self.cr_bitfield = Data(3, "cr_bitfield")
 489         self.cr_bitfield_b = Data(3, "cr_bitfield_b")
 490         self.cr_bitfield_o = Data(3, "cr_bitfield_o")
 491         self.whole_reg = Data(8,  "cr_fxm")
 492
 493     def elaborate(self, platform):
 494         m = Module()
 495         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 496                                                        reverse_o=True)
 497
 498         comb = m.d.comb
 499         op = self.dec.op
 500
 501         comb += self.cr_bitfield.ok.eq(0)
 502         comb += self.cr_bitfield_b.ok.eq(0)
 503         comb += self.whole_reg.ok.eq(0)
 504         with m.Switch(self.sel_in):
 505             with m.Case(CRInSel.NONE):
 506                 pass  # No bitfield activated
 507             with m.Case(CRInSel.CR0):
 508                 comb += self.cr_bitfield.data.eq(0)
 509                 comb += self.cr_bitfield.ok.eq(1)
 510             with m.Case(CRInSel.BI):
 511                 comb += self.cr_bitfield.data.eq(self.dec.BI[2:5])
 512                 comb += self.cr_bitfield.ok.eq(1)
 513             with m.Case(CRInSel.BFA):
 514                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BFA)
 515                 comb += self.cr_bitfield.ok.eq(1)
 516             with m.Case(CRInSel.BA_BB):
 517                 comb += self.cr_bitfield.data.eq(self.dec.BA[2:5])
 518                 comb += self.cr_bitfield.ok.eq(1)
 519                 comb += self.cr_bitfield_b.data.eq(self.dec.BB[2:5])
 520                 comb += self.cr_bitfield_b.ok.eq(1)
 521                 comb += self.cr_bitfield_o.data.eq(self.dec.BT[2:5])
 522                 comb += self.cr_bitfield_o.ok.eq(1)
 523             with m.Case(CRInSel.BC):
 524                 comb += self.cr_bitfield.data.eq(self.dec.BC[2:5])
 525                 comb += self.cr_bitfield.ok.eq(1)
 526             with m.Case(CRInSel.WHOLE_REG):
 527                 comb += self.whole_reg.ok.eq(1)
 528                 move_one = Signal(reset_less=True)
 529                 comb += move_one.eq(self.insn_in[20]) # MSB0 bit 11
 530                 with m.If((op.internal_op == MicrOp.OP_MFCR) & move_one):
 531                     # must one-hot the FXM field
 532                     comb += ppick.i.eq(self.dec.FXM)
 533                     comb += self.whole_reg.data.eq(ppick.o)
 534                 with m.Else():
 535                     # otherwise use all of it
 536                     comb += self.whole_reg.data.eq(0xff)
 537
 538         return m
 539
 540
 541 class DecodeCROut(Elaboratable):
 542     """Decodes input CR from instruction
 543
 544     CR indices - insn fields - (not the data *in* the CR) require only 3
 545     bits because they refer to CR0-CR7
 546     """
 547
 548     def __init__(self, dec):
 549         self.dec = dec
 550         self.rc_in = Signal(reset_less=True)
 551         self.sel_in = Signal(CROutSel, reset_less=True)
 552         self.insn_in = Signal(32, reset_less=True)
 553         self.cr_bitfield = Data(3, "cr_bitfield")
 554         self.whole_reg = Data(8,  "cr_fxm")
 555
 556     def elaborate(self, platform):
 557         m = Module()
 558         comb = m.d.comb
 559         op = self.dec.op
 560         m.submodules.ppick = ppick = PriorityPicker(8, reverse_i=True,
 561                                                        reverse_o=True)
 562
 563         comb += self.cr_bitfield.ok.eq(0)
 564         comb += self.whole_reg.ok.eq(0)
 565         with m.Switch(self.sel_in):
 566             with m.Case(CROutSel.NONE):
 567                 pass  # No bitfield activated
 568             with m.Case(CROutSel.CR0):
 569                 comb += self.cr_bitfield.data.eq(0)
 570                 comb += self.cr_bitfield.ok.eq(self.rc_in)  # only when RC=1
 571             with m.Case(CROutSel.BF):
 572                 comb += self.cr_bitfield.data.eq(self.dec.FormX.BF)
 573                 comb += self.cr_bitfield.ok.eq(1)
 574             with m.Case(CROutSel.BT):
 575                 comb += self.cr_bitfield.data.eq(self.dec.FormXL.BT[2:5])
 576                 comb += self.cr_bitfield.ok.eq(1)
 577             with m.Case(CROutSel.WHOLE_REG):
 578                 comb += self.whole_reg.ok.eq(1)
 579                 move_one = Signal(reset_less=True)
 580                 comb += move_one.eq(self.insn_in[20])
 581                 with m.If((op.internal_op == MicrOp.OP_MTCRF)):
 582                     with m.If(move_one):
 583                         # must one-hot the FXM field
 584                         comb += ppick.i.eq(self.dec.FXM)
 585                         comb += self.whole_reg.data.eq(ppick.o)
 586                     with m.Else():
 587                         comb += self.whole_reg.data.eq(self.dec.FXM)
 588                 with m.Else():
 589                     # otherwise use all of it
 590                     comb += self.whole_reg.data.eq(0xff)
 591
 592         return m
 593
 594
 595 class PowerDecode2(Elaboratable):
 596     """PowerDecode2: the main instruction decoder.
 597
 598     whilst PowerDecode is responsible for decoding the actual opcode, this
 599     module encapsulates further specialist, sparse information and
 600     expansion of fields that is inconvenient to have in the CSV files.
 601     for example: the encoding of the immediates, which are detected
 602     and expanded out to their full value from an annotated (enum)
 603     representation.
 604
 605     implicit register usage is also set up, here.  for example: OP_BC
 606     requires implicitly reading CTR, OP_RFID requires implicitly writing
 607     to SRR1 and so on.
 608
 609     in addition, PowerDecoder2 is responsible for detecting whether
 610     instructions are illegal (or privileged) or not, and instead of
 611     just leaving at that, *replacing* the instruction to execute with
 612     a suitable alternative (trap).
 613     """
 614
 615     def __init__(self, dec):
 616
 617         self.dec = dec
 618         self.e = Decode2ToExecute1Type()
 619
 620         # state information needed by the Decoder (TODO: this as a Record)
 621         self.state = CoreState("dec2")
 622
 623     def ports(self):
 624         return self.dec.ports() + self.e.ports()
 625
 626     def elaborate(self, platform):
 627         m = Module()
 628         comb = m.d.comb
 629         e_out, op, do_out = self.e, self.dec.op, self.e.do
 630         msr, cia = self.state.msr, self.state.pc
 631
 632         # fill in for a normal instruction (not an exception)
 633         # copy over if non-exception, non-privileged etc. is detected
 634         e = Decode2ToExecute1Type()
 635         do = e.do
 636
 637         # set up submodule decoders
 638         m.submodules.dec = self.dec
 639         m.submodules.dec_a = dec_a = DecodeA(self.dec)
 640         m.submodules.dec_b = dec_b = DecodeB(self.dec)
 641         m.submodules.dec_c = dec_c = DecodeC(self.dec)
 642         m.submodules.dec_o = dec_o = DecodeOut(self.dec)
 643         m.submodules.dec_o2 = dec_o2 = DecodeOut2(self.dec)
 644         m.submodules.dec_rc = dec_rc = DecodeRC(self.dec)
 645         m.submodules.dec_oe = dec_oe = DecodeOE(self.dec)
 646         m.submodules.dec_cr_in = dec_cr_in = DecodeCRIn(self.dec)
 647         m.submodules.dec_cr_out = dec_cr_out = DecodeCROut(self.dec)
 648
 649         # copy instruction through...
 650         for i in [do.insn, dec_a.insn_in, dec_b.insn_in,
 651                   dec_c.insn_in, dec_o.insn_in, dec_o2.insn_in, dec_rc.insn_in,
 652                   dec_oe.insn_in, dec_cr_in.insn_in, dec_cr_out.insn_in]:
 653             comb += i.eq(self.dec.opcode_in)
 654
 655         # ...and subdecoders' input fields
 656         comb += dec_a.sel_in.eq(op.in1_sel)
 657         comb += dec_b.sel_in.eq(op.in2_sel)
 658         comb += dec_c.sel_in.eq(op.in3_sel)
 659         comb += dec_o.sel_in.eq(op.out_sel)
 660         comb += dec_o2.sel_in.eq(op.out_sel)
 661         comb += dec_o2.lk.eq(do.lk)
 662         comb += dec_rc.sel_in.eq(op.rc_sel)
 663         comb += dec_oe.sel_in.eq(op.rc_sel)  # XXX should be OE sel
 664         comb += dec_cr_in.sel_in.eq(op.cr_in)
 665         comb += dec_cr_out.sel_in.eq(op.cr_out)
 666         comb += dec_cr_out.rc_in.eq(dec_rc.rc_out.data)
 667
 668         # copy "state" over
 669         comb += do.msr.eq(msr)
 670         comb += do.cia.eq(cia)
 671
 672         # set up instruction, pick fn unit
 673         # no op: defaults to OP_ILLEGAL
 674         comb += do.insn_type.eq(op.internal_op)
 675         comb += do.fn_unit.eq(op.function_unit)
 676
 677         # registers a, b, c and out and out2 (LD/ST EA)
 678         comb += e.read_reg1.eq(dec_a.reg_out)
 679         comb += e.read_reg2.eq(dec_b.reg_out)
 680         comb += e.read_reg3.eq(dec_c.reg_out)
 681         comb += e.write_reg.eq(dec_o.reg_out)
 682         comb += e.write_ea.eq(dec_o2.reg_out)
 683         comb += do.imm_data.eq(dec_b.imm_out)  # immediate in RB (usually)
 684         comb += do.zero_a.eq(dec_a.immz_out)  # RA==0 detected
 685
 686         # rc and oe out
 687         comb += do.rc.eq(dec_rc.rc_out)
 688         comb += do.oe.eq(dec_oe.oe_out)
 689
 690         # SPRs out
 691         comb += e.read_spr1.eq(dec_a.spr_out)
 692         comb += e.write_spr.eq(dec_o.spr_out)
 693
 694         # Fast regs out
 695         comb += e.read_fast1.eq(dec_a.fast_out)
 696         comb += e.read_fast2.eq(dec_b.fast_out)
 697         comb += e.write_fast1.eq(dec_o.fast_out)
 698         comb += e.write_fast2.eq(dec_o2.fast_out)
 699
 700         # condition registers (CR)
 701         comb += e.read_cr1.eq(dec_cr_in.cr_bitfield)
 702         comb += e.read_cr2.eq(dec_cr_in.cr_bitfield_b)
 703         comb += e.read_cr3.eq(dec_cr_in.cr_bitfield_o)
 704         comb += e.write_cr.eq(dec_cr_out.cr_bitfield)
 705
 706         comb += do.read_cr_whole.eq(dec_cr_in.whole_reg)
 707         comb += do.write_cr_whole.eq(dec_cr_out.whole_reg)
 708         comb += do.write_cr0.eq(dec_cr_out.cr_bitfield.ok)
 709
 710         # decoded/selected instruction flags
 711         comb += do.data_len.eq(op.ldst_len)
 712         comb += do.invert_in.eq(op.inv_a)
 713         comb += do.invert_out.eq(op.inv_out)
 714         comb += do.input_carry.eq(op.cry_in)   # carry comes in
 715         comb += do.output_carry.eq(op.cry_out)  # carry goes out
 716         comb += do.is_32bit.eq(op.is_32b)
 717         comb += do.is_signed.eq(op.sgn)
 718         with m.If(op.lk):
 719             comb += do.lk.eq(self.dec.LK)  # XXX TODO: accessor
 720
 721         comb += do.byte_reverse.eq(op.br)
 722         comb += do.sign_extend.eq(op.sgn_ext)
 723         comb += do.ldst_mode.eq(op.upd)  # LD/ST mode (update, cache-inhibit)
 724
 725         # These should be removed eventually
 726         comb += do.input_cr.eq(op.cr_in)   # condition reg comes in
 727         comb += do.output_cr.eq(op.cr_out)  # condition reg goes in
 728
 729         # sigh this is exactly the sort of thing for which the
 730         # decoder is designed to not need.  MTSPR, MFSPR and others need
 731         # access to the XER bits.  however setting e.oe is not appropriate
 732         with m.If(op.internal_op == MicrOp.OP_MFSPR):
 733             comb += e.xer_in.eq(0b111) # SO, CA, OV
 734         with m.If(op.internal_op == MicrOp.OP_CMP):
 735             comb += e.xer_in.eq(1<<XERRegs.SO) # SO
 736         with m.If(op.internal_op == MicrOp.OP_MTSPR):
 737             comb += e.xer_out.eq(1)
 738
 739         # set the trapaddr to 0x700 for a td/tw/tdi/twi operation
 740         with m.If(op.internal_op == MicrOp.OP_TRAP):
 741             # *DO NOT* call self.trap here.  that would reset absolutely
 742             # rverything including destroying read of RA and RB.
 743             comb += do.trapaddr.eq(0x70)    # addr=0x700 (strip first nibble)
 744
 745         # TODO: get msr, then can do privileged instruction
 746         with m.If(instr_is_priv(m, op.internal_op, e.do.insn) & msr[MSR.PR]):
 747             # privileged instruction trap
 748             self.trap(m, TT.PRIV, 0x700)
 749
 750         # illegal instruction must redirect to trap. this is done by
 751         # *overwriting* the decoded instruction and starting again.
 752         # (note: the same goes for interrupts and for privileged operations,
 753         # just with different trapaddr and traptype)
 754         with m.Elif(op.internal_op == MicrOp.OP_ILLEGAL):
 755             # illegal instruction trap
 756             self.trap(m, TT.ILLEG, 0x700)
 757
 758         # no exception, just copy things to the output
 759         with m.Else():
 760             comb += e_out.eq(e)
 761
 762         # trap: (note e.insn_type so this includes OP_ILLEGAL) set up fast regs
 763         # Note: OP_SC could actually be modified to just be a trap
 764         with m.If((do_out.insn_type == MicrOp.OP_TRAP) |
 765                   (do_out.insn_type == MicrOp.OP_SC)):
 766             # TRAP write fast1 = SRR0
 767             comb += e_out.write_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 768             comb += e_out.write_fast1.ok.eq(1)
 769             # TRAP write fast2 = SRR1
 770             comb += e_out.write_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 771             comb += e_out.write_fast2.ok.eq(1)
 772
 773         # RFID: needs to read SRR0/1
 774         with m.If(do_out.insn_type == MicrOp.OP_RFID):
 775             # TRAP read fast1 = SRR0
 776             comb += e_out.read_fast1.data.eq(FastRegs.SRR0)  # constant: SRR0
 777             comb += e_out.read_fast1.ok.eq(1)
 778             # TRAP read fast2 = SRR1
 779             comb += e_out.read_fast2.data.eq(FastRegs.SRR1)  # constant: SRR1
 780             comb += e_out.read_fast2.ok.eq(1)
 781
 782         return m
 783
 784     def trap(self, m, traptype, trapaddr):
 785         """trap: this basically "rewrites" the decoded instruction as a trap
 786         """
 787         comb = m.d.comb
 788         op, do, e = self.dec.op, self.e.do, self.e
 789         comb += e.eq(0)  # reset eeeeeverything
 790
 791         # start again
 792         comb += do.insn.eq(self.dec.opcode_in)
 793         comb += do.insn_type.eq(MicrOp.OP_TRAP)
 794         comb += do.fn_unit.eq(Function.TRAP)
 795         comb += do.trapaddr.eq(trapaddr >> 4)  # cut bottom 4 bits
 796         comb += do.traptype.eq(traptype)  # request type
 797         comb += do.msr.eq(self.state.msr)  # copy of MSR "state"
 798         comb += do.cia.eq(self.state.pc)  # copy of PC "state"
 799
 800
 801 def get_rdflags(e, cu):
 802     rdl = []
 803     for idx in range(cu.n_src):
 804         regfile, regname, _ = cu.get_in_spec(idx)
 805         rdflag, read = regspec_decode_read(e, regfile, regname)
 806         rdl.append(rdflag)
 807     print("rdflags", rdl)
 808     return Cat(*rdl)
 809
 810
 811 if __name__ == '__main__':
 812     pdecode = create_pdecode()
 813     dec2 = PowerDecode2(pdecode)
 814     vl = rtlil.convert(dec2, ports=dec2.ports() + pdecode.ports())
 815     with open("dec2.il", "w") as f:
 816         f.write(vl)