src/soc/decoder/power_enums.py

   1 from enum import Enum, unique
   2 import csv
   3 import os
   4 from os.path import dirname, join
   5 from collections import namedtuple
   6
   7 def find_wiki_file(name):
   8     filedir = os.path.dirname(os.path.abspath(__file__))
   9     basedir = dirname(dirname(dirname(filedir)))
  10     tabledir = join(basedir, 'libreriscv')
  11     tabledir = join(tabledir, 'openpower')
  12     tabledir = join(tabledir, 'isatables')
  13
  14     file_path = join(tabledir, name)
  15     return file_path
  16
  17
  18 def get_csv(name):
  19     file_path = find_wiki_file(name)
  20     with open(file_path, 'r') as csvfile:
  21         reader = csv.DictReader(csvfile)
  22         return list(reader)
  23
  24
  25 # names of the fields in the tables that don't correspond to an enum
  26 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  27                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  28                     'sgn', 'lk', 'sgl pipe']
  29
  30 # default values for fields in the table
  31 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  32                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  33                   'ldst len': 'NONE',
  34                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  35
  36
  37 def get_signal_name(name):
  38     if name[0].isdigit():
  39         name = "is_" + name
  40     return name.lower().replace(' ', '_')
  41
  42
  43 @unique
  44 class Function(Enum):
  45     NONE = 0
  46     ALU = 1
  47     LDST = 2
  48     SHIFT_ROT = 3
  49
  50
  51 @unique
  52 class Form(Enum):
  53     NONE = 0
  54     I = 1
  55     B = 2
  56     SC = 3
  57     D = 4
  58     DS = 5
  59     DQ = 6
  60     DX = 7
  61     X = 8
  62     XL = 9
  63     XFX = 10
  64     XFL = 11
  65     XX1 = 12
  66     XX2 = 13
  67     XX3 = 14
  68     XX4 = 15
  69     XS = 16
  70     XO = 17
  71     A = 18
  72     M = 19
  73     MD = 20
  74     MDS = 21
  75     VA = 22
  76     VC = 23
  77     VX = 24
  78     EVX = 25
  79     EVS = 26
  80     Z22 = 27
  81     Z23 = 28
  82
  83
  84 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
  85 @unique
  86 class InternalOp(Enum):
  87     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
  88     OP_NOP = 1
  89     OP_ADD = 2
  90     OP_ADDPCIS = 3
  91     OP_AND = 4
  92     OP_ATTN = 5
  93     OP_B = 6
  94     OP_BC = 7
  95     OP_BCREG = 8
  96     OP_BPERM = 9
  97     OP_CMP = 10
  98     OP_CMPB = 11
  99     OP_CMPEQB = 12
 100     OP_CMPRB = 13
 101     OP_CNTZ = 14
 102     OP_CRAND = 15
 103     OP_CRANDC = 16
 104     OP_CREQV = 17
 105     OP_CRNAND = 18
 106     OP_CRNOR = 19
 107     OP_CROR = 20
 108     OP_CRORC = 21
 109     OP_CRXOR = 22
 110     OP_DARN = 23
 111     OP_DCBF = 24
 112     OP_DCBST = 25
 113     OP_DCBT = 26
 114     OP_DCBTST = 27
 115     OP_DCBZ = 28
 116     OP_DIV = 29
 117     OP_DIVE = 30
 118     OP_EXTS = 31
 119     OP_EXTSWSLI = 32
 120     OP_ICBI = 33
 121     OP_ICBT = 34
 122     OP_ISEL = 35
 123     OP_ISYNC = 36
 124     OP_LOAD = 37
 125     OP_STORE = 38
 126     OP_MADDHD = 39
 127     OP_MADDHDU = 40
 128     OP_MADDLD = 41
 129     OP_MCRF = 42
 130     OP_MCRXR = 43
 131     OP_MCRXRX = 44
 132     OP_MFCR = 45
 133     OP_MFSPR = 46
 134     OP_MOD = 47
 135     OP_MTCRF = 48
 136     OP_MTSPR = 49
 137     OP_MUL_L64 = 50
 138     OP_MUL_H64 = 51
 139     OP_MUL_H32 = 52
 140     OP_OR = 53
 141     OP_POPCNT = 54
 142     OP_PRTY = 55
 143     OP_RLC = 56
 144     OP_RLCL = 57
 145     OP_RLCR = 58
 146     OP_SETB = 59
 147     OP_SHL = 60
 148     OP_SHR = 61
 149     OP_SYNC = 62
 150     OP_TD = 63
 151     OP_TDI = 64
 152     OP_TW = 65
 153     OP_TWI = 66
 154     OP_XOR = 67
 155     OP_SIM_CONFIG = 68
 156
 157
 158 @unique
 159 class In1Sel(Enum):
 160     NONE = 0
 161     RA = 1
 162     RA_OR_ZERO = 2
 163     SPR = 3
 164
 165
 166 @unique
 167 class In2Sel(Enum):
 168     NONE = 0
 169     RB = 1
 170     CONST_UI = 2
 171     CONST_SI = 3
 172     CONST_UI_HI = 4
 173     CONST_SI_HI = 5
 174     CONST_LI = 6
 175     CONST_BD = 7
 176     CONST_DS = 8
 177     CONST_M1 = 9
 178     CONST_SH = 10
 179     CONST_SH32 = 11
 180     SPR = 12
 181
 182
 183 @unique
 184 class In3Sel(Enum):
 185     NONE = 0
 186     RS = 1
 187
 188
 189 @unique
 190 class OutSel(Enum):
 191     NONE = 0
 192     RT = 1
 193     RA = 2
 194     SPR = 3
 195
 196
 197 @unique
 198 class LdstLen(Enum):
 199     NONE = 0
 200     is1B = 1
 201     is2B = 2
 202     is4B = 3
 203     is8B = 4
 204
 205
 206 @unique
 207 class RC(Enum):
 208     NONE = 0
 209     ONE = 1
 210     RC = 2
 211
 212
 213 @unique
 214 class CryIn(Enum):
 215     ZERO = 0
 216     ONE = 1
 217     CA = 2
 218
 219
 220 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 221 # http://libre-riscv.org/openpower/isatables/sprs.csv
 222 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 223
 224 spr_csv = get_csv("sprs.csv")
 225 spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
 226 spr_dict = {}
 227 for row in spr_csv:
 228     info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 229                     priv_mfspr=row['priv_mfspr'], length=int(row['len']))
 230     spr_dict[int(row['Idx'])] = info
 231 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 232 SPR = Enum('SPR', fields)
 233
 234
 235 XER_bits = {
 236     'SO': 32,
 237     'OV': 33,
 238     'CA': 34,
 239     'OV32': 44,
 240     'CA32': 45
 241     }