src/soc/decoder/power_enums.py

   1 from enum import Enum, unique
   2 import csv
   3 import os
   4 from os.path import dirname, join
   5 from collections import namedtuple
   6
   7 def find_wiki_file(name):
   8     filedir = os.path.dirname(os.path.abspath(__file__))
   9     basedir = dirname(dirname(dirname(filedir)))
  10     tabledir = join(basedir, 'libreriscv')
  11     tabledir = join(tabledir, 'openpower')
  12     tabledir = join(tabledir, 'isatables')
  13
  14     file_path = join(tabledir, name)
  15     return file_path
  16
  17
  18 def get_csv(name):
  19     file_path = find_wiki_file(name)
  20     with open(file_path, 'r') as csvfile:
  21         reader = csv.DictReader(csvfile)
  22         return list(reader)
  23
  24
  25 # names of the fields in the tables that don't correspond to an enum
  26 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  27                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  28                     'sgn', 'lk', 'sgl pipe']
  29
  30 # default values for fields in the table
  31 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  32                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  33                   'ldst len': 'NONE',
  34                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  35
  36
  37 def get_signal_name(name):
  38     if name[0].isdigit():
  39         name = "is_" + name
  40     return name.lower().replace(' ', '_')
  41
  42 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  43 # is to process and guard the operation.  they are roughly divided by having
  44 # the same register input/output signature (X-Form, etc.)
  45 @unique
  46 class Function(Enum):
  47     NONE = 0
  48     ALU = 1
  49     LDST = 2
  50     SHIFT_ROT = 3
  51     LOGICAL = 4
  52     BRANCH = 5
  53
  54
  55 @unique
  56 class Form(Enum):
  57     NONE = 0
  58     I = 1
  59     B = 2
  60     SC = 3
  61     D = 4
  62     DS = 5
  63     DQ = 6
  64     DX = 7
  65     X = 8
  66     XL = 9
  67     XFX = 10
  68     XFL = 11
  69     XX1 = 12
  70     XX2 = 13
  71     XX3 = 14
  72     XX4 = 15
  73     XS = 16
  74     XO = 17
  75     A = 18
  76     M = 19
  77     MD = 20
  78     MDS = 21
  79     VA = 22
  80     VC = 23
  81     VX = 24
  82     EVX = 25
  83     EVS = 26
  84     Z22 = 27
  85     Z23 = 28
  86
  87
  88 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
  89 @unique
  90 class InternalOp(Enum):
  91     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
  92     OP_NOP = 1
  93     OP_ADD = 2
  94     OP_ADDPCIS = 3
  95     OP_AND = 4
  96     OP_ATTN = 5
  97     OP_B = 6
  98     OP_BC = 7
  99     OP_BCREG = 8
 100     OP_BPERM = 9
 101     OP_CMP = 10
 102     OP_CMPB = 11
 103     OP_CMPEQB = 12
 104     OP_CMPRB = 13
 105     OP_CNTZ = 14
 106     OP_CRAND = 15
 107     OP_CRANDC = 16
 108     OP_CREQV = 17
 109     OP_CRNAND = 18
 110     OP_CRNOR = 19
 111     OP_CROR = 20
 112     OP_CRORC = 21
 113     OP_CRXOR = 22
 114     OP_DARN = 23
 115     OP_DCBF = 24
 116     OP_DCBST = 25
 117     OP_DCBT = 26
 118     OP_DCBTST = 27
 119     OP_DCBZ = 28
 120     OP_DIV = 29
 121     OP_DIVE = 30
 122     OP_EXTS = 31
 123     OP_EXTSWSLI = 32
 124     OP_ICBI = 33
 125     OP_ICBT = 34
 126     OP_ISEL = 35
 127     OP_ISYNC = 36
 128     OP_LOAD = 37
 129     OP_STORE = 38
 130     OP_MADDHD = 39
 131     OP_MADDHDU = 40
 132     OP_MADDLD = 41
 133     OP_MCRF = 42
 134     OP_MCRXR = 43
 135     OP_MCRXRX = 44
 136     OP_MFCR = 45
 137     OP_MFSPR = 46
 138     OP_MOD = 47
 139     OP_MTCRF = 48
 140     OP_MTSPR = 49
 141     OP_MUL_L64 = 50
 142     OP_MUL_H64 = 51
 143     OP_MUL_H32 = 52
 144     OP_OR = 53
 145     OP_POPCNT = 54
 146     OP_PRTY = 55
 147     OP_RLC = 56
 148     OP_RLCL = 57
 149     OP_RLCR = 58
 150     OP_SETB = 59
 151     OP_SHL = 60
 152     OP_SHR = 61
 153     OP_SYNC = 62
 154     OP_TD = 63
 155     OP_TDI = 64
 156     OP_TW = 65
 157     OP_TWI = 66
 158     OP_XOR = 67
 159     OP_SIM_CONFIG = 68
 160
 161
 162 @unique
 163 class In1Sel(Enum):
 164     NONE = 0
 165     RA = 1
 166     RA_OR_ZERO = 2
 167     SPR = 3
 168
 169
 170 @unique
 171 class In2Sel(Enum):
 172     NONE = 0
 173     RB = 1
 174     CONST_UI = 2
 175     CONST_SI = 3
 176     CONST_UI_HI = 4
 177     CONST_SI_HI = 5
 178     CONST_LI = 6
 179     CONST_BD = 7
 180     CONST_DS = 8
 181     CONST_M1 = 9
 182     CONST_SH = 10
 183     CONST_SH32 = 11
 184     SPR = 12
 185
 186
 187 @unique
 188 class In3Sel(Enum):
 189     NONE = 0
 190     RS = 1
 191
 192
 193 @unique
 194 class OutSel(Enum):
 195     NONE = 0
 196     RT = 1
 197     RA = 2
 198     SPR = 3
 199
 200
 201 @unique
 202 class LdstLen(Enum):
 203     NONE = 0
 204     is1B = 1
 205     is2B = 2
 206     is4B = 3
 207     is8B = 4
 208
 209
 210 @unique
 211 class RC(Enum):
 212     NONE = 0
 213     ONE = 1
 214     RC = 2
 215
 216
 217 @unique
 218 class CryIn(Enum):
 219     ZERO = 0
 220     ONE = 1
 221     CA = 2
 222
 223
 224 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 225 # http://libre-riscv.org/openpower/isatables/sprs.csv
 226 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 227
 228 spr_csv = get_csv("sprs.csv")
 229 spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
 230 spr_dict = {}
 231 for row in spr_csv:
 232     info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 233                     priv_mfspr=row['priv_mfspr'], length=int(row['len']))
 234     spr_dict[int(row['Idx'])] = info
 235 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 236 SPR = Enum('SPR', fields)
 237
 238
 239 XER_bits = {
 240     'SO': 32,
 241     'OV': 33,
 242     'CA': 34,
 243     'OV32': 44,
 244     'CA32': 45
 245     }