src/soc/decoder/power_enums.py

   1 from enum import Enum, unique
   2 import csv
   3 import os
   4 from os.path import dirname, join
   5 from collections import namedtuple
   6
   7 def find_wiki_file(name):
   8     filedir = os.path.dirname(os.path.abspath(__file__))
   9     basedir = dirname(dirname(dirname(filedir)))
  10     tabledir = join(basedir, 'libreriscv')
  11     tabledir = join(tabledir, 'openpower')
  12     tabledir = join(tabledir, 'isatables')
  13
  14     file_path = join(tabledir, name)
  15     return file_path
  16
  17
  18 def get_csv(name):
  19     file_path = find_wiki_file(name)
  20     with open(file_path, 'r') as csvfile:
  21         reader = csv.DictReader(csvfile)
  22         return list(reader)
  23
  24
  25 # names of the fields in the tables that don't correspond to an enum
  26 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  27                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  28                     'sgn', 'lk', 'sgl pipe']
  29
  30 # default values for fields in the table
  31 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  32                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  33                   'ldst len': 'NONE',
  34                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  35
  36
  37 def get_signal_name(name):
  38     if name[0].isdigit():
  39         name = "is_" + name
  40     return name.lower().replace(' ', '_')
  41
  42 # this corresponds to which Function Unit (pipeline-with-Reservation-Stations)
  43 # is to process and guard the operation.  they are roughly divided by having
  44 # the same register input/output signature (X-Form, etc.)
  45 @unique
  46 class Function(Enum):
  47     NONE = 0
  48     ALU = 1
  49     LDST = 2
  50     SHIFT_ROT = 3
  51     LOGICAL = 4
  52     BRANCH = 5
  53     CR = 6
  54
  55
  56 @unique
  57 class Form(Enum):
  58     NONE = 0
  59     I = 1
  60     B = 2
  61     SC = 3
  62     D = 4
  63     DS = 5
  64     DQ = 6
  65     DX = 7
  66     X = 8
  67     XL = 9
  68     XFX = 10
  69     XFL = 11
  70     XX1 = 12
  71     XX2 = 13
  72     XX3 = 14
  73     XX4 = 15
  74     XS = 16
  75     XO = 17
  76     A = 18
  77     M = 19
  78     MD = 20
  79     MDS = 21
  80     VA = 22
  81     VC = 23
  82     VX = 24
  83     EVX = 25
  84     EVS = 26
  85     Z22 = 27
  86     Z23 = 28
  87
  88
  89 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
  90 @unique
  91 class InternalOp(Enum):
  92     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
  93     OP_NOP = 1
  94     OP_ADD = 2
  95     OP_ADDPCIS = 3
  96     OP_AND = 4
  97     OP_ATTN = 5
  98     OP_B = 6
  99     OP_BC = 7
 100     OP_BCREG = 8
 101     OP_BPERM = 9
 102     OP_CMP = 10
 103     OP_CMPB = 11
 104     OP_CMPEQB = 12
 105     OP_CMPRB = 13
 106     OP_CNTZ = 14
 107     OP_CRAND = 15
 108     OP_CRANDC = 16
 109     OP_CREQV = 17
 110     OP_CRNAND = 18
 111     OP_CRNOR = 19
 112     OP_CROR = 20
 113     OP_CRORC = 21
 114     OP_CRXOR = 22
 115     OP_DARN = 23
 116     OP_DCBF = 24
 117     OP_DCBST = 25
 118     OP_DCBT = 26
 119     OP_DCBTST = 27
 120     OP_DCBZ = 28
 121     OP_DIV = 29
 122     OP_DIVE = 30
 123     OP_EXTS = 31
 124     OP_EXTSWSLI = 32
 125     OP_ICBI = 33
 126     OP_ICBT = 34
 127     OP_ISEL = 35
 128     OP_ISYNC = 36
 129     OP_LOAD = 37
 130     OP_STORE = 38
 131     OP_MADDHD = 39
 132     OP_MADDHDU = 40
 133     OP_MADDLD = 41
 134     OP_MCRF = 42
 135     OP_MCRXR = 43
 136     OP_MCRXRX = 44
 137     OP_MFCR = 45
 138     OP_MFSPR = 46
 139     OP_MOD = 47
 140     OP_MTCRF = 48
 141     OP_MTSPR = 49
 142     OP_MUL_L64 = 50
 143     OP_MUL_H64 = 51
 144     OP_MUL_H32 = 52
 145     OP_OR = 53
 146     OP_POPCNT = 54
 147     OP_PRTY = 55
 148     OP_RLC = 56
 149     OP_RLCL = 57
 150     OP_RLCR = 58
 151     OP_SETB = 59
 152     OP_SHL = 60
 153     OP_SHR = 61
 154     OP_SYNC = 62
 155     OP_TD = 63
 156     OP_TDI = 64
 157     OP_TW = 65
 158     OP_TWI = 66
 159     OP_XOR = 67
 160     OP_SIM_CONFIG = 68
 161
 162
 163 @unique
 164 class In1Sel(Enum):
 165     NONE = 0
 166     RA = 1
 167     RA_OR_ZERO = 2
 168     SPR = 3
 169
 170
 171 @unique
 172 class In2Sel(Enum):
 173     NONE = 0
 174     RB = 1
 175     CONST_UI = 2
 176     CONST_SI = 3
 177     CONST_UI_HI = 4
 178     CONST_SI_HI = 5
 179     CONST_LI = 6
 180     CONST_BD = 7
 181     CONST_DS = 8
 182     CONST_M1 = 9
 183     CONST_SH = 10
 184     CONST_SH32 = 11
 185     SPR = 12
 186
 187
 188 @unique
 189 class In3Sel(Enum):
 190     NONE = 0
 191     RS = 1
 192
 193
 194 @unique
 195 class OutSel(Enum):
 196     NONE = 0
 197     RT = 1
 198     RA = 2
 199     SPR = 3
 200
 201
 202 @unique
 203 class LdstLen(Enum):
 204     NONE = 0
 205     is1B = 1
 206     is2B = 2
 207     is4B = 3
 208     is8B = 4
 209
 210
 211 @unique
 212 class RC(Enum):
 213     NONE = 0
 214     ONE = 1
 215     RC = 2
 216
 217
 218 @unique
 219 class CryIn(Enum):
 220     ZERO = 0
 221     ONE = 1
 222     CA = 2
 223
 224
 225 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 226 # http://libre-riscv.org/openpower/isatables/sprs.csv
 227 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 228
 229 spr_csv = get_csv("sprs.csv")
 230 spr_info = namedtuple('spr_info', 'SPR priv_mtspr priv_mfspr length')
 231 spr_dict = {}
 232 for row in spr_csv:
 233     info = spr_info(SPR=row['SPR'], priv_mtspr=row['priv_mtspr'],
 234                     priv_mfspr=row['priv_mfspr'], length=int(row['len']))
 235     spr_dict[int(row['Idx'])] = info
 236 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 237 SPR = Enum('SPR', fields)
 238
 239
 240 XER_bits = {
 241     'SO': 32,
 242     'OV': 33,
 243     'CA': 34,
 244     'OV32': 44,
 245     'CA32': 45
 246     }