src/soc/decoder/power_enums.py

   1 from enum import Enum, unique
   2 import csv
   3 import os
   4 import requests
   5
   6
   7 def download_wiki_file(name, name_on_wiki=None):
   8     if name_on_wiki is None:
   9         name_on_wiki = name
  10     file_dir = os.path.dirname(os.path.realpath(__file__))
  11     file_path = os.path.join(file_dir, name)
  12     if not os.path.isfile(file_path):
  13         url = 'https://libre-riscv.org/openpower/isatables/' + name_on_wiki
  14         r = requests.get(url, allow_redirects=True)
  15         with open(file_path, 'w') as outfile:
  16             outfile.write(r.content.decode("utf-8"))
  17     return file_path
  18
  19
  20 def get_csv(name):
  21     file_path = download_wiki_file(name)
  22     with open(file_path, 'r') as csvfile:
  23         reader = csv.DictReader(csvfile)
  24         return list(reader)
  25
  26
  27 # names of the fields in the tables that don't correspond to an enum
  28 single_bit_flags = ['CR in', 'CR out', 'inv A', 'inv out',
  29                     'cry out', 'BR', 'sgn ext', 'upd', 'rsrv', '32b',
  30                     'sgn', 'lk', 'sgl pipe']
  31
  32 # default values for fields in the table
  33 default_values = {'unit': "NONE", 'internal op': "OP_ILLEGAL",
  34                   'in1': "RA", 'in2': 'NONE', 'in3': 'NONE', 'out': 'NONE',
  35                   'ldst len': 'NONE',
  36                   'rc': 'NONE', 'cry in': 'ZERO', 'form': 'NONE'}
  37
  38
  39 def get_signal_name(name):
  40     if name[0].isdigit():
  41         name = "is_" + name
  42     return name.lower().replace(' ', '_')
  43
  44
  45 @unique
  46 class Function(Enum):
  47     NONE = 0
  48     ALU = 1
  49     LDST = 2
  50
  51
  52 @unique
  53 class Form(Enum):
  54     NONE = 0
  55     I = 1
  56     B = 2
  57     SC = 3
  58     D = 4
  59     DS = 5
  60     DQ = 6
  61     DX = 7
  62     X = 8
  63     XL = 9
  64     XFX = 10
  65     XFL = 11
  66     XX1 = 12
  67     XX2 = 13
  68     XX3 = 14
  69     XX4 = 15
  70     XS = 16
  71     XO = 17
  72     A = 18
  73     M = 19
  74     MD = 20
  75     MDS = 21
  76     VA = 22
  77     VC = 23
  78     VX = 24
  79     EVX = 25
  80     EVS = 26
  81     Z22 = 27
  82     Z23 = 28
  83
  84
  85 # Internal Operation numbering.  Add new opcodes here (FPADD, FPMUL etc.)
  86 @unique
  87 class InternalOp(Enum):
  88     OP_ILLEGAL = 0     # important that this is zero (see power_decoder.py)
  89     OP_NOP = 1
  90     OP_ADD = 2
  91     OP_ADDPCIS = 3
  92     OP_AND = 4
  93     OP_ATTN = 5
  94     OP_B = 6
  95     OP_BC = 7
  96     OP_BCREG = 8
  97     OP_BPERM = 9
  98     OP_CMP = 10
  99     OP_CMPB = 11
 100     OP_CMPEQB = 12
 101     OP_CMPRB = 13
 102     OP_CNTZ = 14
 103     OP_CRAND = 15
 104     OP_CRANDC = 16
 105     OP_CREQV = 17
 106     OP_CRNAND = 18
 107     OP_CRNOR = 19
 108     OP_CROR = 20
 109     OP_CRORC = 21
 110     OP_CRXOR = 22
 111     OP_DARN = 23
 112     OP_DCBF = 24
 113     OP_DCBST = 25
 114     OP_DCBT = 26
 115     OP_DCBTST = 27
 116     OP_DCBZ = 28
 117     OP_DIV = 29
 118     OP_DIVE = 30
 119     OP_EXTS = 31
 120     OP_EXTSWSLI = 32
 121     OP_ICBI = 33
 122     OP_ICBT = 34
 123     OP_ISEL = 35
 124     OP_ISYNC = 36
 125     OP_LOAD = 37
 126     OP_STORE = 38
 127     OP_MADDHD = 39
 128     OP_MADDHDU = 40
 129     OP_MADDLD = 41
 130     OP_MCRF = 42
 131     OP_MCRXR = 43
 132     OP_MCRXRX = 44
 133     OP_MFCR = 45
 134     OP_MFSPR = 46
 135     OP_MOD = 47
 136     OP_MTCRF = 48
 137     OP_MTSPR = 49
 138     OP_MUL_L64 = 50
 139     OP_MUL_H64 = 51
 140     OP_MUL_H32 = 52
 141     OP_OR = 53
 142     OP_POPCNT = 54
 143     OP_PRTY = 55
 144     OP_RLC = 56
 145     OP_RLCL = 57
 146     OP_RLCR = 58
 147     OP_SETB = 59
 148     OP_SHL = 60
 149     OP_SHR = 61
 150     OP_SYNC = 62
 151     OP_TD = 63
 152     OP_TDI = 64
 153     OP_TW = 65
 154     OP_TWI = 66
 155     OP_XOR = 67
 156     OP_SIM_CONFIG = 68
 157
 158
 159 @unique
 160 class In1Sel(Enum):
 161     NONE = 0
 162     RA = 1
 163     RA_OR_ZERO = 2
 164     SPR = 3
 165
 166
 167 @unique
 168 class In2Sel(Enum):
 169     NONE = 0
 170     RB = 1
 171     CONST_UI = 2
 172     CONST_SI = 3
 173     CONST_UI_HI = 4
 174     CONST_SI_HI = 5
 175     CONST_LI = 6
 176     CONST_BD = 7
 177     CONST_DS = 8
 178     CONST_M1 = 9
 179     CONST_SH = 10
 180     CONST_SH32 = 11
 181     SPR = 12
 182
 183
 184 @unique
 185 class In3Sel(Enum):
 186     NONE = 0
 187     RS = 1
 188
 189
 190 @unique
 191 class OutSel(Enum):
 192     NONE = 0
 193     RT = 1
 194     RA = 2
 195     SPR = 3
 196
 197
 198 @unique
 199 class LdstLen(Enum):
 200     NONE = 0
 201     is1B = 1
 202     is2B = 2
 203     is4B = 3
 204     is8B = 4
 205
 206
 207 @unique
 208 class RC(Enum):
 209     NONE = 0
 210     ONE = 1
 211     RC = 2
 212
 213
 214 @unique
 215 class CryIn(Enum):
 216     ZERO = 0
 217     ONE = 1
 218     CA = 2
 219
 220
 221 # SPRs - Special-Purpose Registers.  See V3.0B Figure 18 p971 and
 222 # http://libre-riscv.org/openpower/isatables/sprs.csv
 223 # http://bugs.libre-riscv.org/show_bug.cgi?id=261
 224
 225 spr_csv = get_csv("sprs.csv")
 226 fields = [(row['SPR'], int(row['Idx'])) for row in spr_csv]
 227 SPR = Enum('SPR', fields)